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参数资料
| 型号： | 935267488112 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 20 MHz, MICROCONTROLLER, PDSO20 |
| 封装： | 7.50 MM, PLASTIC, SO-20 |
| 文件页数： | 4/69页 |
| 文件大小： | 352K |
| 代理商： | 935267488112 |
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Philips Semiconductors
Preliminary specification
87LPC768
Low power, low price, low pin count (20 pin) microcontroller with
4 kB OTP 8-bit A/D, Pulse Width Modulator
2000 May 02
10
ADCON
Address: C0h
Bit addressable
Reset Value: 00h
BIT
SYMBOL
FUNCTION
ADCON.7
ENADC
When ENADC = 1, the A/D is enabled and conversions may take place. Must be set 10
microseconds before a conversion is started. ENADC cannot be cleared while ADCS or ADCI
are 1.
ADCON.6
-
Reserved for future use. Should not be set to 1 by user programs.
ADCON.5
-
Reserved for future use. Should not be set to 1 by user programs.
ADCON.4
ADCI
A/D conversion complete/interrupt flag. This flag is set when an A/D conversion is completed.
This bit will cause a hardware interrupt if enabled and of sufficient priority. Must be cleared by
software.
ADCON.3
ADCS
A/D start. Setting this bit by software starts the conversion of the selected A/D input. ADCS
remains set while the A/D conversion is in progress and is cleared automatically upon
completion. While ADCS or ADCI are one, new start commands are ignored.
ADCI, ADCS
A/D Status
0 0
A/D not busy, a conversion can be started.
0 1
A/D busy, the start of a new conversion is blocked.
1 0
An A/D conversion is complete. ADCI must be cleared prior to starting a new conversion.
1 1
An A/D conversion is complete. ADCI must be cleared prior to starting a new conversion. This
state exists for one machine cycle as an A/D conversion is completed.
ADCON.2
RCCLK
When RCCLK = 0, the CPU clock is used as the A/D clock. When RCCLK = 1, the internal RC
oscillator is used as the A/D clock. This bit is writable while ADCS and ADCI are 0.
ADCON.1, 0
AADR1,0
Along with AADR0, selects the A/D channel to be converted. These bits can only be written
while ADCS and ADCI are 0.
AADR1, AADR0
A/D Input Selected
0 0
AD0 (P0.3).
0 1
AD1 (P0.4).
1 0
AD2 (P0.5).
1 1
AD3 (P0.6).
7
6
54
32
10
ENADC
-
ADCI
ADCS
RCCLK
AADR1
AADR0
SU01354
Figure 2. A/D Control Register (ADCON)
A/D Timing
The A/D may be clocked in one of two ways. The default is to use
the CPU clock as the A/D clock source. When used in this manner,
the A/D completes a conversion in 31 machine cycles. The A/D may
be operated up to the maximum CPU clock rate of 20 MHz, giving a
conversion time of 9.3
s. The formula for calculating A/D
conversion time when the CPU clock runs the A/D is: 186
s / CPU
clock rate (in MHZ). To obtain accurate A/D conversion results, the
CPU clock must be at least 1 MHz.
The A/D may also be clocked by the on-chip RC oscillator, even if
the RC oscillator is not used as the CPU clock. This is accomplished
by setting the RCCLK bit in ADCON. This arrangement has several
advantages. First, the A/D conversion time is faster at lower CPU
clock rates. Also, the CPU may be run at speeds below 1 MHz
without affecting A/D accuracy. Finally, the Power Down mode may
be used to completely shut down the CPU and its oscillator, along
with other peripheral functions, in order to obtain the best possible
A/D accuracy. This should not be used if the MCU uses an external
clock source greater than 4 MHz.
When the A/D is operated from the RCCLK while the CPU is running
from another clock source, 3 or 4 machine cycles are used to
synchronize A/D operation. The time can range from a minimum of 3
machine cycles (at the CPU clock rate) + 108 RC clocks to a
maximum of 4 machine cycles (at the CPU clock rate) + 112 RC
clocks.
Example A/D conversion times at various CPU clock rates are
shown in Table 2. In Table 2, maximum times for RCCLK = 1 use an
RC clock frequency of 4.5 MHz (6 MHz - 25%). Minimum times for
RCCLK = 1 use an RC clock frequency of 7.5 MHz (6 MHz + 25%).
Nominal time assume an ideal RC clock frequency of 6 MHz and an
average of 3.5 machine cycles at the CPU clock rate.
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