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参数资料
| 型号： | 951901AFLF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 133.34 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, GREEN, MO-118, SSOP-48 |
| 文件页数： | 17/21页 |
| 文件大小： | 206K |
| 代理商： | 951901AFLF |
5
ICS951901
0670B—07/15/04
Byte 6: Control , Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
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B-
0
d
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v
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R
6
t
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B-
0
d
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R
5
t
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1
d
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v
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4
t
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B-
0
d
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3
t
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1
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2
t
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0
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1
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0
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1
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R
Byte 7: Vendor ID Register
(1= enable, 0 = disable)
T
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B#
N
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PD
W
PN
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7
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20
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,
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=
0
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6
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=
1
Byte 8: Byte Count and Read Back Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
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R
C
S
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7
t
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0
d
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6
t
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0
d
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5
t
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0
d
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v
r
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s
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4
t
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B-
0
d
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v
r
e
s
e
R
3
t
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B-
0
d
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v
r
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s
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R
2
t
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B-
1
d
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v
r
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s
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R
1
t
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B-
0
d
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v
r
e
s
e
R
0
t
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B-
0
d
e
v
r
e
s
e
R
Note: FS values in bit [0:4] will correspond to Byte 0 FS
values. Default safe frequency is same as 00000
entry in byte0.
Byte 10: VCO Control Selection Bit &
Watchdog Timer Control Register
t
i
BD
W
Pn
o
i
t
p
i
r
c
s
e
D
7
t
i
B0
q
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2
1
&
1
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=
1
/
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f
0
B
/
w
H
=
0
6
t
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b
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5
t
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=
1
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=
0
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W
4
t
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2
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0
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3
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3
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2
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2
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1
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1
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0
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F
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W
Byte 9: Watchdog Timer Count Register
t
i
BD
W
Pn
o
i
t
p
i
r
c
s
e
D
7
t
i
B0
e
s
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T
s
m
1
r
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s
m
0
9
2
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t
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8
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q
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6
.
4
=
s
m
0
9
2
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6
1
s
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w
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p
t
a
.
s
d
n
o
c
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s
6
t
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B0
5
t
i
B0
4
t
i
B1
3
t
i
B0
2
t
i
B0
1
t
i
B0
0
t
i
B0
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相关代理商/技术参数 |
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| 951901AFLFT | 制造商:Integrated Device Technology Inc 功能描述:Programmable PLL Frequency Generator Dual 48-Pin SSOP T/R |
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