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参数资料
| 型号： | 951901AFLF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 133.34 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, GREEN, MO-118, SSOP-48 |
| 文件页数： | 9/21页 |
| 文件大小： | 206K |
| 代理商： | 951901AFLF |
17
ICS951901
0670B—07/15/04
SDRAM_STOP# Timing Diagram
SDRAM_STOP# is an asychronous input to the clock synthesizer. It is used to stop SDRAM clocks for low power
operation. SDRAM_STOP# is synchronized to complete it's current cycle, by the ICS94209. All other clocks will
continue to run while the SDRAM clocks are disabled. The SDRAM clocks will always be stopped in a low state and
start in such a manner that guarantees the high pulse width is a full pulse.
Notes:
1. All timing is referenced to the internal CPU clock.
2. SDRAM is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the SDRAM clocks inside the ICS94209.
3. All other clocks continue to run undisturbed.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 951901AFLFT | 制造商:Integrated Device Technology Inc 功能描述:Programmable PLL Frequency Generator Dual 48-Pin SSOP T/R |
| 951902 | 制造商:Weidmuller 功能描述:WPG-M25, CABLE GLAND, PA,BLA -EA - Bulk |
| 951903 | 制造商:Weidmuller 功能描述:WPG-M32, CABLE GLAND, PA,BLA -EA - Bulk |
| 951904 | 制造商:Weidmuller 功能描述:WPG-M40, CABLE GLAND, PA,BLA -EA - Bulk |
| 951905 | 制造商:Weidmuller 功能描述:WPG-M50, CABLE GLAND, PA,BLA -EA - Bulk |
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