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| 型号： | A3985SLDTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 11/15页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET DRVR PROG DUAL 38TSSOP |
| 标准包装： | 1 |
| 配置： | 半桥 |
| 输入类型： | 非反相 |
| 延迟时间： | 120ns |
| 配置数： | 2 |
| 输出数： | 8 |
| 电源电压： | 12 V ~ 50 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 38-TSSOP |
| 包装： | 标准包装 |
| 产品目录页面： | 1141 (CN2011-ZH PDF) |
| 其它名称： | 620-1180-6 |
A3985
Digitally Programmable
Dual Full-Bridge MOSFET Driver
to 0 disables Bridge 1, with all drivers off (see Internal PWM
Current Control, in the Functional Description section).
D7 – Bridge 1 Phase Controls the direction of output cur-
rent for Bridge (load) 1.
Control Register (Word 1) Bit Assignments
This section describes the function of the individual bit val-
ues in the Control register, one of the two registers accessed
through the serial port. The assignments are summarized in
D7
0
1
S1A
L
H
S1B
H
L
the Bit Assignments table.
Note that the Control register can only be updated when the
WC pin is logic low.
D8 – Bridge 1 Mode Determines whether slow decay is
forced or mixed decay, according to Word 1 Bits D3 to D11,
is allowed.
D8 Mode
0 Mixed-decay
1 Slow-decay
D9 – D14 Bridge 2 Linear DAC These six bits set the
D0 – Register Select Indicates which register should
receive the data. For the Control register, this is set to 1.
D1 and D2 – Blank Time These two bits set the value of
the scaling factor, ? / f MCK , used for determining t BLANK for
the current-sense comparator. The factor for t DEAD also is set,
because t DEAD = t BLANK / 2 .
desired current level for Bridge 2. Setting all six bits to 0
D2
D1
t BLANK
t DEAD
disables Bridge 2, with all drivers off (see Internal PWM
(t BLANK / 2)
Current Control, in the Functional Description section).
D15 – Bridge 2 Phase Controls the direction of output
current for Bridge (load) 2.
0
0
1
0
1
0
4 / f MCK
6 / f MCK
8 / f MCK
2 / f MCK
3 / f MCK
4 / f MCK
D15
S2A
S2B
1
1
12 / f MCK
6 / f MCK
0
1
L
H
H
L
D3 through D7 – Fixed Off Time These five bits set the
fixed off-time for the internal PWM control circuitry. Fixed
D16 – Bridge 2 Mode Determines whether slow decay is
forced or mixed decay, according to Word 1 Bits D3 to D11,
is allowed.
D16 Mode
off-time is defined by:
t OFF = [(1 + n ) × (8 / f MCK )] – 1 / f MCK ,
where n = 0 to 31.
0
1
Mixed-decay
Slow-decay
For example, with a master clock frequency of 4 MHz, the
fixed off-time time would be adjustable within the range
D17 and D18 – G m Range Select These bits determine
the range scaling factor, G m , used in PWM current control,
according to the following formula:
I TripDAC = V DAC / (G m × R SENSE x )
1.75 to 63.75 μ s, in increments of 2 μ s.
D8 through D11 – Fast Decay Time These four bits set
the fast decay portion of fixed off-time for the internal PWM
control circuitry. The fast-decay portion is defined by:
D18
0
0
1
1
D17
0
1
0
1
G m
8
12
16
20
t FD = [(1 + n ) × 8 / f MCK )] – 1 / f MCK ,
where n = 0 to 15.
For example, with a master clock frequency of 4 MHz, the
fast decay time would be adjustable within the range
1.75 to 32.75 μ s, in increments of 2 μ s.
Allegro MicroSystems, LLC
115 Northeast Cutoff
11
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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