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| 型号： | A3985SLDTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 13/15页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET DRVR PROG DUAL 38TSSOP |
| 标准包装： | 1 |
| 配置： | 半桥 |
| 输入类型： | 非反相 |
| 延迟时间： | 120ns |
| 配置数： | 2 |
| 输出数： | 8 |
| 电源电压： | 12 V ~ 50 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 38-TSSOP |
| 包装： | 标准包装 |
| 产品目录页面： | 1141 (CN2011-ZH PDF) |
| 其它名称： | 620-1180-6 |
A3985
Digitally Programmable
Dual Full-Bridge MOSFET Driver
Applications Information
Current Sensing
To minimize inaccuracies in sensing the I PEAK current
level caused by ground-trace IR drops, the sense resistor,
RSENSE x , should have an independent return to the supply
ground star point. For low-value sense resistors, the IR drops
in the sense resistor PCB traces can be significant and should
be taken into account. The use of sockets should be avoided
as they can introduce variation in RENSE S x due to their
contact resistance.
Thermal Protection
All drivers are turned off when the junction temperature
reaches 165°C typical. This is intended only to protect the
A3985 from failures due to excessive junction temperatures.
Thermal protection will not protect the A3985 from continu-
ous short circuits. Thermal shutdown has a hysteresis of
approximately 15°C.
Circuit Layout
Since this is a switch-mode application, where rapid current
changes are present, care must be taken during layout of the
application PCB. The following points are provided as guid-
ance for layout. Following all guidelines will not always be
possible. However, each point should be carefully considered
as part of any layout procedure.
Ground Connection Layout Recommendations:
1. Decoupling capacitors for the supply pins VBB, VREG,
and VDD should be connected independently, close to the
GND pin, and not to any ground plane. The decoupling
capacitors should also be connected as close as possible to
the corresponding supply pin.
2. If used, the oscillator timing resistor ROSC should be
connected to the GND pin. It should not be connected to any
ground plane, supply common, or the power ground.
3. The GND pin should be connected by an independent low-
impedance trace to the supply common at a single point.
4. Check the peak voltage excursion of the transients on
the LSS pin with reference to the GND pin using a close
grounded (tip and barrel) probe. If the voltage at LSS
exceeds the specified absolute maximum add additional
clamping, capacitance, or both, between the LSS pin and the
AGND pin.
Other layout recommendations:
1. Gate charge drive paths and gate discharge return paths
may carry transient current pulses. Therefore, the traces from
GH xx , GL xx , S xx , and LSS x should be as short as possible to
reduce the inductance of the circuit trace.
2. Provide an independent connection from each LSS pin
to the common point of each power bridge. It is not recom-
mended to connect LSS directly to the GND pin. The LSS
connection should not be used for the SENSE connection.
3. Minimize stray inductance by using short, wide copper
runs at the drain and source terminals of all power FETs.
This includes motor lead connections, the input power bus,
and the common source of the low-side power FETs. This
will minimize voltages induced by fast switching of large
load currents.
4. Consider the use of small (100nF) ceramic decoupling
capacitors across the source and drain of the power FETs to
limit fast transient voltage spikes caused by trace inductance.
The above are only recommendations. Each application is
different and may encounter different sensitivities. Each
design should be tested at the maximum current, to ensure
any parasitic effects are eliminated.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13
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