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参数资料
| 型号： | A3985SLDTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 12/15页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET DRVR PROG DUAL 38TSSOP |
| 标准包装： | 1 |
| 配置： | 半桥 |
| 输入类型： | 非反相 |
| 延迟时间： | 120ns |
| 配置数： | 2 |
| 输出数： | 8 |
| 电源电压： | 12 V ~ 50 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 38-TSSOP |
| 包装： | 标准包装 |
| 产品目录页面： | 1141 (CN2011-ZH PDF) |
| 其它名称： | 620-1180-6 |
A3985
Note that, for t FD > t OFF , the device effectively operates in
full fast-decay mode.
Digitally Programmable
Dual Full-Bridge MOSFET Driver
modes are described in the synchronous rectification section
of the Functional Description section.
D12 and D13 – Master Clock Control An internal
oscillator can be used for the timing functions, and if more
precise control is required, an external clock can be input to
the OSC terminal (for configuration information, refer to the
Functional Description section). To accommodate a wider
range of external system clocks, an internal divider is pro-
D15
0
0
1
D14
0
1
0
Synchronous
Rectification Mode
Disabled
Disabled
Active
vided to generate the desired master clock frequency, f MCK ,
according to the following table:
1 1 Passive
D16 and D17 – Reserved These bits are reserved for
D13
0
0
1
1
D12
0
1
0
1
Master Clock Source and f MCK
Internal oscillator*
External clock rate
External clock rate / 2
External clock rate / 4
testing and should be programmed to 0 during normal
operation.
D18 – Idle Mode The device can be placed in a low
power mode by writing a 0 to D18. This disables the VREG
regulator (to 0 V) and the outputs, and the device draws a
lower load supply current. The undervoltage monitor circuit
*4 MHz typical, configurable with external resistor, ROSC.
D14 and D15 – Synchronous Rectification Two bits
are used to set the mode for synchronous rectification. The
Bit Assignments Table
Data Register
remains active. When leaving idle mode, D18 should be set
to 1 for at least 1 ms to allow the regulator to return VREG
to its normal operating voltage ( ≈ 12 V) before attempting to
enable any output driver.
Control Register
Word Bit Function
D0 Register Select = 0
D1 Bridge 1, DAC bit 0 (LSB)
D2 Bridge 1, DAC bit 1
D3 Bridge 1, DAC bit 2
D4 Bridge 1, DAC bit 3
D5 Bridge 1, DAC bit 4
D6 Bridge 1, DAC bit 5 (MSB)
D7 Bridge 1, Phase
D8 Bridge 1, Mode
Word
Bit
D0
D1
D2
D3
D4
D5
D6
D7
D8
Function
Register Select = 1
Blank-time bit 0 (LSB)
Blank-time bit 1 (MSB)
Off-time bit 0 (LSB)
Off-time bit 1
Off-time bit 2
Off-time bit 3
Off-time bit 4 (MSB)
Fast-decay time bit 0 (LSB)
0
D9 Bridge 2, DAC bit 0 (LSB)
D10 Bridge 2, DAC bit 1
D11 Bridge 2, DAC bit 2
D12 Bridge 2, DAC bit 3
D13 Bridge 2, DAC bit 4
D14 Bridge 2, DAC bit 5 (MSB)
D15 Bridge 2, Phase
D16 Bridge 2, Mode
D17 Range Select bit 0
D18 Range Select bit 1
1
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
Fast-decay time bit 1
Fast-decay time bit 2
Fast-decay time bit 3 (MSB)
Master Clock Control bit 0 (LSB)
Master Clock Control bit 1 (MSB)
Synchronous Rectification Control bit 0 (LSB)
Synchronous Rectification Control bit 1 (MSB)
Reserved
Reserved
Idle Mode
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
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