- 您现在的位置：买卖IC网 > Datasheet目录306 > A3985SLDTR-T (Allegro Microsystems Inc)IC MOSFET DRVR PROG DUAL 38TSSOP Datasheet资料下载
参数资料
| 型号： | A3985SLDTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 7/15页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET DRVR PROG DUAL 38TSSOP |
| 标准包装： | 1 |
| 配置： | 半桥 |
| 输入类型： | 非反相 |
| 延迟时间： | 120ns |
| 配置数： | 2 |
| 输出数： | 8 |
| 电源电压： | 12 V ~ 50 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 38-TSSOP |
| 包装： | 标准包装 |
| 产品目录页面： | 1141 (CN2011-ZH PDF) |
| 其它名称： | 620-1180-6 |
A3985
Digitally Programmable
Dual Full-Bridge MOSFET Driver
Functional Description
Basic Operation
The A3985 is a highly-configurable dual full-bridge FET
driver with built-in digital current control. All features are
accessed through a simple SPI (Serial Peripheral Interface)
compatible serial port, allowing multiple motors to be con-
trolled with as few as three wires.
Because the full-bridge control circuits are independently
controlled, the A3985 can be used to drive 2-phase bipolar
stepper motors and 2-phase brushless dc (BLDC) motors.
The current in each of the two external power full-bridges
(which are all N-channel MOSFETs) is regulated by a fixed
off-time PWM control circuit. The full-bridge current at each
step is set by the value of an external current sense resistor,
R SENSE X , in the ground connection to the bridge, a reference
voltage, V REF , and the output of the DAC controlled by the
serial data.
The use of PWM with N-channel MOSFETs provides the
most cost-effective solution for a high efficiency motor drive.
The A3985 provides all the necessary circuits to ensure
that the gate-source voltage of both high-side and low-side
external MOSFETs are above 10 V, and that there is no cross-
conduction (shoot through) in the external bridge. Specific
functions are described more fully in the following sections.
Power Supplies
Two power connections are required. The motor power sup-
ply should be connected to VBB to provide the gate drive
levels. Power for internal logic is provided by the VDD
input. Internal logic is designed to operate from 3 to 5.5 V,
allowing the use of 3.3 or 5 V external logic interface cir-
cuits.
GND The ground pin is a reference voltage for internal logic
and analog circuits. There is no large current flow through
this pin. To avoid any noise from switching circuits, this
should have an independent trace to the supply ground star
point.
VREG The voltage at this pin is generated by a low-drop-out
linear regulator from the VBB supply. It is used to oper-
ate the low-side gate drive outputs, GL xx , and to provide
the charging current for the bootstrap capacitors, CBOOT x .
To limit the voltage drop when the charge current is pro-
vided, this pin should be decoupled with a ceramic capaci-
tor, CREG, to ground. The value C REG should typically
be 40 times the value of the bootstrap capacitor for PWM
frequencies up to 14 kHz. Above 14 kHz, the minimum
recommended value can be determined from the following
formula:
C REG > C BOOT × 3 × f PWM ,
where C REG and C BOOT are in nF, and f PWM is the maximum
PWM frequency, in kHz. V REG is monitored, and if the volt-
age becomes too low, the outputs will be disabled.
REF The reference voltage, V REF , at this pin sets the
maximum (100%) peak current. The REF input is internally
limited to 2 V when a 20 k ?? pull-up resistor is connected
between VREF and VDD . This allows the maximum refer-
ence voltage to be set without the need for an externally-
generated voltage. An external reference voltage below the
maximum can also be input on this pin. The voltage at VREF
is divided by the range select ratio G m to produce the DAC
reference voltage level.
OSC The PWM timing is based on a master clock, typically
running at 4 MHz. The master clock period is used to derive
the PWM off-time, dead time, and blanking time.
The master clock frequency can be set by an internal oscil-
lator or by one of three division ratios of an external clock.
These four options are selected by bits D12 and D13 of the
Control register word.
When the A3985 is configured to use an external clock,
this is input on the OSC pin and will usually provide more
precision than using the internal oscillator. The three internal
divider alternatives provide flexibility in setting the master
clock frequency based on available external system clocks.
If internal timing is selected, f OSC is configured by using
an external resistor, ROSC, connected from the OSC pin to
GND. This sets the frequency (in MHz) to approximately:
f OSC ≈ 100 / (6 + 1.9 × R OSC ) ,
where R OSC , in k ? , is typically between 50 k ? and 10 k ? .
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
相关PDF资料 |
PDF描述 |
|---|---|
| A4933KJPTR-T | IC PREDRIVER MOSFET 3PH 48LQFP |
| A4935KJPTR-T | IC MOSFET DVR AUTO 3PH 48-LQFP |
| A4940KLPTR-T | IC MOSF DVR FULL BRIDGE 24TSSOP |
| A6210GEUTR-T | IC LED DRIVER HIGH BRIGHT 16-QFN |
| A6261KLPTR-T | IC LED ARRAY DVR 400MA 16-TSSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A3986 | 制造商:ALLEGRO 制造商全称:Allegro MicroSystems 功能描述:Dual Full-Bridge MOSFET Driver with Microstepping Translator |
| A3986_12 | 制造商:ALLEGRO 制造商全称:Allegro MicroSystems 功能描述:Dual Full-Bridge MOSFET Driver with Microstepping Translator |
| A3986SLD-T | 制造商:Allegro MicroSystems 功能描述:DUAL FULL-BRIDGE MOSFET DRIVER WITH MICROSTEPPING TRANSLATOR 制造商:Allegro MicroSystems 功能描述:IC MOTOR DRIVER |
| A3986SLDTR-T | 功能描述:IC DRIVER MICROSTEPPING 38-TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 电机和风扇控制器，驱动器 系列:- 标准包装:1 系列:- 应用:步进电机驱动器，1-2 相，2 相 评估套件:- 输出数:1 电流 - 输出:800mA 电压 - 负载:10 V ~ 28 V 电源电压:4.75 V ~ 5.25 V 工作温度:-20°C ~ 90°C 安装类型:表面贴装 封装/外壳:28-SOP + 2 翼片裸露焊盘 供应商设备封装:28-HSOPHC（15.2x7.9） 包装:剪切带 (CT) 其它名称:869-1268-1 |
| A3987 | 制造商:ALLEGRO 制造商全称:Allegro MicroSystems 功能描述:DMOS Microstepping Driver with Translator |
发布紧急采购，3分钟左右您将得到回复。