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参数资料
| 型号： | A3P-L67201V-55 |
| 厂商： | ATMEL WIRELESS MICROCONTROLLERS |
| 元件分类： | FIFO |
| 英文描述： | 512 X 9 OTHER FIFO, 55 ns, PDIP28 |
| 封装： | 0.300 INCH, PLASTIC, DIP-28 |
| 文件页数： | 1/16页 |
| 文件大小： | 146K |
| 代理商： | A3P-L67201V-55 |
L 67201/L 67202
MATRA MHS
Rev. C (10/11/95)
1
Introduction
The L67201/202 implement a first-in first-out algorithm,
featuring asynchronous read/write operations. The FULL
and EMPTY flags prevent data overflow and underflow.
The Expansion logic allows unlimited expansion in word
size and depth with no timing penalties. Twin address
pointers automatically generate internal read and write
addresses, and no external address information are
required for the MHS FIFOs. Address pointers are
automatically incremented with the write pin and read
pin. The 9 bits wide data are used in data communications
applications where a parity bit for error checking is
necessary. The Retransmit pin reset the Read pointer to
zero without affecting the write pointer. This is very
useful for retransmitting data when an error is detected in
the system.
Using an array of eight transistors (8 T) memory cell and
fabricated with the state of the art 1.0
m lithography
named SCMOS, the L 67201/202 combine an extremely
low standby supply current (typ = 1.0
A) with a fast
access time at 55 ns over the full temperature range. All
versions offer battery backup data retention capability
with a typical power consumption at less than 5
W.
For military/space applications that demand superior
levels of performance and reliability the L 67201/202 is
processed according to the methods of the latest revision
of the MIL STD 883 (class B or S) and/or ESA SCC 9000.
Features
D First-in first-out dual port memory
D Single supply 3.3 ± 0.3 volts
D 512 × 9 organisation (L 67201)
D 1024 × 9 organisation (L 67202)
D Fast access time
55, 60, 65 ns, commercial, industrial military and
automotive
D Wide temperature range :
– 55
°C to + 125 °C
D 67201L/202L low power
67201V/202V very low power
D Fully expandable by word width or depth
D Asynchronous read/write operations
D Empty, full and half flags in single device mode
D Retransmit capability
D Bi-directional applications
D Battery back-up operation 2 V data retention
D TTL compatible
D High performance SCMOS technology
512
× 9 & 1K × 9 / 3.3 Volts CMOS Parallel FIFO
相关PDF资料 |
PDF描述 |
|---|---|
| A3P-L67202L-65 | 1K X 9 OTHER FIFO, 65 ns, PDIP28 |
| ASI-L67201L-60 | 512 X 9 OTHER FIFO, 60 ns, PQCC32 |
| ATIR0721DS | POSITION, LINEAR SENSOR-DIFFUSE, 1-1mm, 3mA, RECTANGULAR, SURFACE MOUNT |
| ATIR0821DS | POSITION, LINEAR SENSOR-DIFFUSE, 1-1mm, 3mA, RECTANGULAR, THROUGH HOLE MOUNT |
| ATL80/25-256VM | FPGA, 15600 GATES |
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