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| 型号： | A4933KJPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 13/25页 |
| 文件大小： | 0K |
| 描述： | IC PREDRIVER MOSFET 3PH 48LQFP |
| 标准包装： | 4,500 |
| 配置： | 3 相桥 |
| 输入类型： | PWM |
| 延迟时间： | 90ns |
| 配置数： | 1 |
| 输出数： | 3 |
| 电源电压： | 5.5 V ~ 50 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP 裸露焊盘 |
| 供应商设备封装： | 48-LQFP |
| 包装： | 带卷 (TR) |
A4933
Automotive 3-Phase MOSFET Driver
the output from the comparators are ignored under two condi-
tions:
? while the external FET is off, and
? until the end of the period, referred to as the fault blank time ,
after the FET is turned on.
When the FET is turned on, if the drain-source voltage exceeds
the voltage at the VDSTH pin at any time after the fault blank
time, then a short fault will be detected. If also ESF is set high,
then this fault will be latched and the FET disabled until reset.
In some applications, the fault blank time may be insufficient to
avoid detecting false faults during the switching time of the exter-
nal FET. In these cases, the external controller driving the A4933
may be used to determine the correct fault condition by setting
ESF low. This will prevent latching of the fault flag when a short
fault is detected, and will not disable the FET. With ESF low, FF2
will remain high only while the measured V DS exceeds the fault
threshold. The external controller can then monitor the fault flags
and use its own timers to validate a fault condition.
Note that any fault thus detected by the A4933 will still be
latched in the fault register and remain there until cleared.
When ESF is set low, the external FETs are not disabled by the
A4933 when a short fault is detected. To avoid permanent dam-
age to the external FETs or to the motor under this condition, the
A4933 can either be fully disabled by the RESET input or all
FETs can be switched off by pulling low the COAST input or all
the phase control inputs.
Short to Supply A short from any of the motor phase connec-
tions to the battery or VBB connection is detected by monitoring
the voltage across the low-side FETs in each phase, using the
appropriate Sx pin and the LSS pin. This drain-source voltage,
V DS , is continuously compared to the voltage on the VDSTH pin.
The result of this comparison is ignored if the FET is not active.
It is ignored also for one fault blank time interval after the FET is
turned on. If, when the comparator is not being ignored, its output
indicates that V DS exceeds the voltage at the VDSTH pin, then
FF2 will be high. If also ESF is set high, then FF2 will be latched
high and the outputs will be disabled. Alternatively, if also ESF
is set low, then the outputs will not be disabled and FF2 will only
be high while the output of the comparator indicates that V DS
exceeds the voltage at the VDSTH pin.
Short to Ground A short from any of the motor phase connec-
tions to ground is detected by monitoring the voltage across the
high-side FETs in each phase, using the appropriate Sx pin and
the voltage at VDRAIN. This drain-source voltage, V DS , is con-
tinuously compared to the voltage on the VDSTH pin. The result
of this comparison is ignored if the FET is not active. It is ignored
also for one fault blank time interval after the FET is turned on.
If, when the comparator is not being ignored, its output indicates
that V DS exceeds the voltage at the VDSTH pin, FF2 will be high.
If also ESF is set high, FF2 will be latched high and the outputs
will be disabled. Alternatively, if also ESF is set low, the outputs
will not be disabled and FF2 will only be high while the output
of the comparator indicates that V DS exceeds the voltage at the
VDSTH pin.
Shorted Load The short-to-ground and short-to-supply monitor
circuits will also detect a short across a motor phase winding. In
most cases, a shorted winding will be indicated by a high-side
and low-side fault being detected at the same time. In some cases
the relative impedances may permit only one of the shorts to be
detected.
Differentiating Short Fault Conditions
The distinction between short-to-ground, short-to-supply, and
shorted load can only be made by examining the contents of the
fault register. It is not possible to determine where a short fault
has occurred when using the state of the fault flags, FF1 and
FF2, alone. The flag combination FF1 low and FF2 high simply
indicates the presence of a probable short circuit.
As described above, shorts are detected by monitoring the drain-
source voltage, V DS , of each of the six FETs in the power bridge.
The different short fault conditions are defined as follows:
? A short-to-ground is likely to be present if the V DS of any active
high-side FET is greater than the threshold defined by VDSTH
(fault bits AH, BH, or CH = 1)
? A short-to-supply is likely to be present if the V DS of any active
low-side FET is greater than the threshold defined by VDSTH
(fault bits AL, BL, or CL = 1)
? A shorted load or phase is likely to be present if, at the same
time, the V DS of an active high-side and an active low-side are
both greater than the threshold defined by VDSTH.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13
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