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参数资料
| 型号： | A4933KJPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 20/25页 |
| 文件大小： | 0K |
| 描述： | IC PREDRIVER MOSFET 3PH 48LQFP |
| 标准包装： | 4,500 |
| 配置： | 3 相桥 |
| 输入类型： | PWM |
| 延迟时间： | 90ns |
| 配置数： | 1 |
| 输出数： | 3 |
| 电源电压： | 5.5 V ~ 50 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP 裸露焊盘 |
| 供应商设备封装： | 48-LQFP |
| 包装： | 带卷 (TR) |
A4933
Automotive 3-Phase MOSFET Driver
The A4933 can also be used to perform regenerative braking.
This is equivalent to reversing the motor commutation sequence
tor, RG, between CSP and AGND also have matched values. The
gain of the sense amplfier, G, is determined by the relative values
R F
G =
or using fast decay with synchronous rectification. Note that
phase commutation must continue for regenerative braking to
operate and the supply must be capable of managing the reverse
current, such as by connecting a resistive load or dumping the
of RF and RN, and is approximately:
,
R N
(11)
current to a battery or capacitor.
Current Sense Amplifier
The gain of the current sense amplifier is set using external input
and feedback resistors. Output offset can also be added using
external resistors. Care must be taken to ensure that the input
impedances seen from either end of the sense resistor match.
For the basic configuration shown in figure 4A, the two input
resistors, RN and RP, have matched values. The feedback resistor,
RF, between CSN and CSOUT, and the ground reference resis-
If an output offset is required, for example to allow reverse cur-
rent measurement, then this can be generated by adding offset to
the CSP input through the RG resistor. Because the amplifier is
operating in a closed loop, any offset added to CSP will be mir-
rored at the output.
Figure 4B shows suitable resistor values for a gain, G, of 20 and
an output offset, V OS , of 250 mV.
Layout Recommendations
Careful consideration must be given to PCB layout when design-
ing high frequency, fast switching, high current circuits. The
R S
R P
CSP
R F
A4933
CSOUT
following are recommendations regarding some of these consid-
erations:
? The A4933 analog ground, AGND, and power ground, PGND,
should be connected together at the package pins. This common
point, and the high-current return of the external FETs, should
R N
R G
CSN
G = R F / R N
R G = R F
R P = R N
(A) Basic configuration
return separately to the negative side of the motor supply
filtering capacitor. This will minimize the effect of switching
noise on the device logic and analog reference.
? The exposed thermal pad and all NC pins of the package should
be connected to the common point of AGND and PGND.
? Minimize stray inductance by using short, wide copper traces at
the drain and source terminals of all power FETs. This includes
80 k Ω
motor lead connections, the input power bus, and the common
source of the low-side power FETs. This will minimize voltages
4 k Ω
A4933
induced by fast switching of large load currents.
R S
4 k Ω
5V
76 k Ω
CSP
CSN
76 k Ω
4 k Ω
CSOUT
G = 20
V OS = 250 mV
? Consider the use of small (100 nF) ceramic decoupling
capacitors across the sources and drains of the power FETs to
limit fast transient voltage spikes caused by the inductance of
the circuit trace.
? Keep the gate discharge return connections Sx and LSS as short
as possible. Any inductance on these traces will cause negative
transitions on the corresponding A4933 pins, which may exceed
the absolute maximum ratings. If this is likely, consider the use
(B) Typical Configuration
Figure 4. Current sense amplifier configurations
of clamping diodes to limit the negative excursion on these pins
with respect to AGND.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
20
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