参数资料
型号: A4933KJPTR-T
厂商: Allegro Microsystems Inc
文件页数: 19/25页
文件大小: 0K
描述: IC PREDRIVER MOSFET 3PH 48LQFP
标准包装: 4,500
配置: 3 相桥
输入类型: PWM
延迟时间: 90ns
配置数: 1
输出数: 3
电源电压: 5.5 V ~ 50 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 48-LQFP 裸露焊盘
供应商设备封装: 48-LQFP
包装: 带卷 (TR)
A4933
Automotive 3-Phase MOSFET Driver
tor (>1000 nF). If the bootstrap capacitor voltage does not reach
the threshold within approximately 200 μ s, an undervoltage fault
will be flagged.
attention should be paid to ensure the operating conditions allow
the A4933 to remain in a safe range of junction temperature.
The power consumed by the A4933, P D , can be estimated by:
VREG Capacitor Selection
The internal reference, VREG, supplies current for the low-side
given:
P D = P BIAS + P CPUMP + P SWITCHING ,
(6)
gate drive circuits and the charging current for the bootstrap
capacitors. When a low-side FET is turned on, the gate-drive
circuit will provide the high transient current to the gate that is
necessary to turn on the FET quickly. This current, which can be
several hundred milliamperes, cannot be provided directly by the
P BIAS = V BB × I BB ;
P CPUMP = [( 2 V BB ) – V REG ] I AV
or
= [ V BB – V REG ] I AV
, for V BB < 15 V,
, for V BB ≥ 15 V,
(7)
(8)
limited output of the VREG regulator, and must be supplied by an
external capacitor connected to VREG.
P SWITCHING = Q GATE × V REG × N × f PWM × Ratio ;
(9)
Ratio =
10
The turn-on current for the high-side FETis similar in value to
that for the low-side FET, but is mainly supplied by the boot-
strap capacitor. However the bootstrap capacitor must then be
recharged from the VREG regulator output. Unfortunately the
bootstrap recharge can occur a very short time after the low-
side turn-on occurs. This requires that the value of the capacitor
connected between VREG and AGND should be high enough to
minimize the transient voltage drop on VREG for the combina-
tion of a low-side FET turn-on and a bootstrap capacitor recharge.
A value of 20 × C BOOT is a reasonable value. The maximum
working voltage will never exceed V REG , so the capacitor can be
rated as low as 15 V. This capacitor should be placed as close as
possible to the VREG pin.
Supply Decoupling
Because this is a switching circuit, there are current spikes from all
where:
I AV = Q GATE × N × f PWM ,
N is the number of FETs switching during a PWM cycle, and
.
R GATE + 10
Braking
The A4933 can be used to perform dynamic braking by either
forcing all low-side FETs on and all high-side FETs off or, con-
versely, by forcing all low-side FETs off and all high-side FETs
on. This will effectively short-circuit the back EMF of the motor,
creating a breaking torque.
During braking, the load current can be approximated by:
supplies at the switching points. As with all such circuits, the power
supply connections should be decoupled with a ceramic capacitor,
typically 100 nF, between the supply pin and ground. These capaci-
I BRAKE =
V BEMF
R L
,
(10)
tors should be connected as close as possible to the device supply
pins VBB and VDD, and the power ground pin, PGND.
Power Dissipation
In applications where a high ambient temperature is expected, the
on-chip power dissipation may become a critical factor. Careful
where V BEMF is the voltage generated by the motor and R L is the
resistance of the phase winding.
Care must be taken during braking to ensure that the maximum
ratings of the power FETs are not exceeded. Dynamic braking is
equivalent to slow decay with synchronous rectification and all
phases enabled.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
19
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