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| 型号： | A4933KJPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 14/25页 |
| 文件大小： | 0K |
| 描述： | IC PREDRIVER MOSFET 3PH 48LQFP |
| 标准包装： | 4,500 |
| 配置： | 3 相桥 |
| 输入类型： | PWM |
| 延迟时间： | 90ns |
| 配置数： | 1 |
| 输出数： | 3 |
| 电源电压： | 5.5 V ~ 50 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP 裸露焊盘 |
| 供应商设备封装： | 48-LQFP |
| 包装： | 带卷 (TR) |
A4933
Fault Register
Automotive 3-Phase MOSFET Driver
then an under voltage has been detected. In either case, the
All undervoltage and short faults are recorded in a 10-bit fault
register as defined in table 3. The fault register accumulates all
detected faults until cleared by setting RESET low, by cycling the
power off and on, or by reading the contents. The contents will
also be cleared if a VDD undervoltage fault is detected. During a
VDD undervoltage fault condition, both fault flags will be high
but all the bits in the fault register will be reset.
Table 3. Fault Register Bit Definitions
Bit Position Function
AH First V DS exceeded on A phase high-side FET
BH 2 V DS exceeded on B phase high-side FET
CH 3 V DS exceeded on C phase high-side FET
sequence for reading the contents of the fault register is:
1. The external controller takes any necessary additional action to
protect the FETs.
2. The external controller pulls FF2 low.
3. The A4933 outputs on FF1 the fault register first bit, AH.
4. The external controller reads the fault bit, and then cycles FF2
high then low for the next bit, BH.
5. Steps 3 and 4 alternate until all of the 10 bits in the fault regis-
ter have been read out.
6. After the final bit, VC, is output, the external controller cycles
FF2 high then low.
AL
BL
CL
VR
VA
VB
VC
4
5
6
7
8
9
Last
V DS exceeded on A phase low-side FET
V DS exceeded on B phase low-side FET
V DS exceeded on C phase low-side FET
Undervoltage detected on VREG
Bootstrap undervoltage detected on phase A
Bootstrap undervoltage detected on phase B
Bootstrap undervoltage detected on phase C
7. The A4933 resets the fault register and pulls FF1 and FF2 low
to indicate no fault present.
8. The external controller releases FF2.
The basic sequence for the three possible states of FF1 and FF2
are shown in figure 1.
At the end of the serial transfer, on the last high-to-low transition
input to FF2, the fault register and the fault flags are reset. How-
The contents of the fault register can be read serially from the
FF1 pin by applying a clock signal to the FF2 pin during an
undervoltage or short fault state.
The fault flag pins, FF1 and FF2, are open drain outputs and pas-
sively pulled high when a fault is present. This makes it possible
to drive one or both of these fault pins from an external source
during a fault condition, when the A4933 is not pulling the pin
low. FF2 can thus be used as a clock input to shift out the fault
status register, bit-by-bit, on the other fault flag, FF1.
When FF2 is being pulled low by the A4933, either when no fault
is present or when an overtemperature fault is present, then no
serial access is possible. The fault status register can be accessed
only when FF2 goes high. This occurs when either a short or an
undervoltage fault has been detected.
Faut Register Serial Access
To access the fault register, FF1 and FF2 must be monitored by
an external controller. If FF2 goes high and FF1 remains low,
then a short has been detected. If FF1 and FF2 go high together,
ever, it is possible that one of the three unlatched fault conditions,
VREG undervoltage, VDD undervoltage, or overtemperature, is
still present. In this case the fault flags will immediately show the
fault status.
Resetting the VR Bit
At power-up, on coming out of reset, or after a VDD or VREG
undervoltage fault, it is possible that the fault flags and fault reg-
ister will have cleared but the VR bit in the fault register remains
set. This would happen if, when a power-on-reset occurred,
V REG had not yet risen beyond the undervoltage threshold level,
V REGUVon . Although VREG undervoltage fault state is not latched
and the fault flags are cleared when the fault is removed, the
VR bit in the fault register is latched and may remain set after
the power-on-reset. For this reason it is recommended, when the
serial fault register is to be used, to perform a reset by taking the
RESET pin low for less than the reset pulse time, t RES , after the
A4933 is powered-up and all fault flags are clear (FF1 and FF2
are low).
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
14
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