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参数资料
| 型号： | A4940KLPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 11/14页 |
| 文件大小： | 0K |
| 描述： | IC MOSF DVR FULL BRIDGE 24TSSOP |
| 标准包装： | 1 |
| 配置： | 半桥 |
| 输入类型： | 非反相 |
| 延迟时间： | 35ns |
| 配置数： | 1 |
| 输出数： | 4 |
| 电源电压： | 5.5 V ~ 50 V |
| 工作温度： | -40°C ~ 150°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 供应商设备封装： | 24-TSSOP 裸露焊盘 |
| 包装： | 标准包装 |
| 产品目录页面： | 1141 (CN2011-ZH PDF) |
| 其它名称： | 620-1319-6 |
A4940
Supply Decoupling
Automotive Full Bridge MOSFET Driver
are recommendations regarding some of these considerations:
Because this is a switching circuit, there are current spikes from
all supplies at the switching points. As with all such circuits, the
power supply connections should be decoupled with a ceramic
capacitor, typically 100 nF, between the supply pin and ground.
These capacitors should be connected as close as possible to the
device supply pins, VDD and VBB, and the ground pin, GND.
Power Dissipation
In applications where a high ambient temperature is expected the
on-chip power dissipation may become a critical factor. Careful
attention should be paid to ensure the operating conditions allow
the A4940 to remain in a safe range of junction temperature.
The power consumed by the A4940, P D , can be estimated by :
P D = P BIAS + P CPUMP + P SWITCHING
given
P BIAS = V BB × I BB
P CPUMP = [(2 × V BB ) – V REG ) × I av for V BB < 15 V
P CPUMP = ( V BB – V REG ) × I av for V BB > 15 V
I av = Q GATE × N × f PWM
P SWITCHING = Q GATE × V REG × N × f PWM × Ratio
Ratio = 10 / (R GATE + 10)
where N is the quantity of MOSFETs switching during a PWM
cycle. N = 1 for slow decay with diode recirculation, N = 2 for slow
decay with synchronous rectification or fast decay with diode recir-
culation, and N = 4 for fast decay with synchronous rectification.
Layout Recommendations
Careful consideration must be given to PCB layout when designing
high frequency, fast switching, high current circuits. The following
? The A4940 ground, GND, and the high-current return of the ex-
ternal MOSFETs should return separately to the negative side of
the motor supply filtering capacitor. This minimizes the effect
of switching noise on the device logic and analog reference.
? The exposed thermal pad should be connected to the GND pin
and may form part of the Controller Supply ground (see figure 2).
? Minimize stray inductance by using short, wide copper traces at
the drain and source terminals of all power MOSFETs. This in-
cludes motor lead connections, the input power bus, and the com-
mon source of the low-side power MOSFETs. This will minimize
voltages induced by fast switching of large load currents.
? Consider the use of small (100 nF) ceramic decoupling capaci-
tors across the sources and drains of the power MOSFETs to
limit fast transient voltage spikes caused by the inductance of
the circuit trace.
? The ground connection to RDEAD should be connected inde-
pendently directly to the AGND pin. This sensitive component
should never be connected directly to the supply common or to
a common ground plane. It must be referenced directly to the
AGND pin.
? Supply decoupling for VBB, VREG, and VDD should be con-
nected to the Controller Supply ground which is independently
connected close to the GND pin. The decoupling capacitors should
also be connected as close as possible to the relevant supply pin.
Note that the above are only recommendations. Each application
is different and may encounter different sensitivities. A driver
running a few amps will be less susceptible than one running with
150 A and each design should be tested at the maximum current
to ensure any parasitic effects are eliminated.
Optional reverse battery protection
VBB
GHB
VREG
GHA
A4940
+ Supply
VDD
RDEAD
SA
SB
GLA
GLB
Motor
R DEAD
AGND GND
Controller Supply Ground
Figure 2. Supply routing suggestions
Power Ground
Supply
Common
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
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