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参数资料
| 型号： | A4940KLPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 7/14页 |
| 文件大小： | 0K |
| 描述： | IC MOSF DVR FULL BRIDGE 24TSSOP |
| 标准包装： | 1 |
| 配置： | 半桥 |
| 输入类型： | 非反相 |
| 延迟时间： | 35ns |
| 配置数： | 1 |
| 输出数： | 4 |
| 电源电压： | 5.5 V ~ 50 V |
| 工作温度： | -40°C ~ 150°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 供应商设备封装： | 24-TSSOP 裸露焊盘 |
| 包装： | 标准包装 |
| 产品目录页面： | 1141 (CN2011-ZH PDF) |
| 其它名称： | 620-1319-6 |
A4940
Automotive Full Bridge MOSFET Driver
on the upper half of the drive, sourcing current to the gate of the
high-side MOSFET in the external motor-driving bridge, turning
it on. GHx going low turns on the lower half of the drive, sinking
current from the external MOSFET gate circuit to the correspond-
ing Sx pin, turning off the MOSFET.
CA and CB Pins These are the high-side connections for the
bootstrap capacitors and are the positive supply for the high-side
gate drives. The bootstrap capacitors are charged to approxi-
mately V REG when the associated output Sx terminal is low.
When the Sx output swings high, the charge on the bootstrap
capacitor causes the voltage at the corresponding Cx terminal to
rise with the output to provide the boosted gate voltage needed
for the high-side MOSFETs.
RDEAD Pin This pin controls internal generation of dead time
during MOSFET switching. Cross-conduction is prevented
by the gate drive circuits, which introduce a dead time, t DEAD ,
between switching one MOSFET off and the complementary
MOSFET on.
? When an external resistor greater than 3 k Ω is connected be-
tween RDEAD and AGND, the dead time is derived from the
resistor value.
? When RDEAD is connected directly to VDD, t DEAD defaults to
a value of 6 μ s typical.
Logic Control Inputs
Four low voltage-level digital inputs provide control for the gate
drives. These logic inputs all have a typical hysteresis of 500 mV
to improve noise performance. They provide individual direct
control over each power MOSFET, subject to cross-conduction
prevention, and can be used together to provide fast decay or
slow decay with high-side or low-side recirculation.
AHI, ALO, BHI and BLO Pins These directly control the gate
drives. The xHI inputs control the high-side drives and the xLO
Table 1. Input Logic
inputs control the low-side drives. Internal lockout logic ensures
that the high-side output drive and low-side output drive cannot
be active simultaneously. Table 1 shows the logic truth table.
RESET Pin This is an active-low input, and when active it
allows the A4940 to enter sleep mode. When RESET is held low,
the regulator and all internal circuitry are disabled and the A4940
enters sleep mode. Before fully entering sleep mode, there is a
short delay while the regulator decoupling and storage capacitors
discharge. This typically takes a few milliseconds, depending on
the application conditions and component values.
During sleep mode, current consumption from the VBB supply
is reduced to a minimal level. In addition, latched faults and the
corresponding fault flags are cleared. When the A4940 is coming
out of sleep mode, the protection logic ensures that the gate drive
outputs are off until the charge pump reaches its correct operat-
ing condition. The charge pump stabilizes in approximately 3 ms
under nominal conditions.
RESET can be used also to clear latched fault flags without enter-
ing sleep mode. To do so, hold RESET low for the reset pulse
time, t RES . This clears the latched bootstrap capacitor undervolt-
age fault that disables the outputs.
Note that the A4940 can be configured to start without any exter-
nal logic input. To do so, pull up the RESET pin to V BB by means
of an external resistor. The resistor value should be between
20 and 33 k Ω .
Diagnostics
Several diagnostic features are integrated into the A4940 to
provide indication of fault conditions. In addition to system wide
faults such as undervoltage and overtemperature, the A4940 inte-
grates individual bootstrap voltage monitors for each bootstrap
capacitor.
RESET
xHI
Pin Setting
xLO GHx
GLx
Sx
Mode of Operation
H
H
H
H
L
H
L
H
L
x
L
H
H
L
x
H
L
L
L
Z
L
H
H
L
Z
H
L
L
Z
Z
High side MOSFET conducting
Low Side MOSFET conducting
Low Side MOSFET conducting – cross-conduction prevention
High side and low side off
All gate drives inactive, all MOSFETs off
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
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