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参数资料
| 型号： | A4940KLPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 14/14页 |
| 文件大小： | 0K |
| 描述： | IC MOSF DVR FULL BRIDGE 24TSSOP |
| 标准包装： | 1 |
| 配置： | 半桥 |
| 输入类型： | 非反相 |
| 延迟时间： | 35ns |
| 配置数： | 1 |
| 输出数： | 4 |
| 电源电压： | 5.5 V ~ 50 V |
| 工作温度： | -40°C ~ 150°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 供应商设备封装： | 24-TSSOP 裸露焊盘 |
| 包装： | 标准包装 |
| 产品目录页面： | 1141 (CN2011-ZH PDF) |
| 其它名称： | 620-1319-6 |
A4940
Automotive Full Bridge MOSFET Driver
Package LP 24-Pin TSSOP with Exposed Thermal Pad
24
7.80±0.10
8o
0o
0.45
0.65
0.20
0.09
B
3 NOM
4.40±0.10
6.40±0.20
3.00
6.10
0.60 ±0.15
A
1.00 REF
24X
0.10 C
1
2
4.32 NOM
SEATING
PLANE
C
0.25 BSC
SEATING PLANE
GAUGE PLANE
1.65
C
4.32
PCB Layout Reference View
0.30
0.19
0.65 BSC
0.15
0.00
1.20 MAX
For Reference Only; not for tooling use (reference MO-153 ADT)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B
Exposed thermal pad (bottom surface); dimensions may vary with device
C Reference land pattern layout (reference IPC7351
TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all
adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a multilayer
PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
Copyright ?2010-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
14
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