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参数资料
| 型号： | A63L73321SERIES |
| 元件分类： | 通用总线功能 |
| 英文描述： | 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output |
| 中文描述： | 128K的× 32位同步计数器高的Burst SRAM的速度和流量，通过数据输出 |
| 文件页数： | 13/17页 |
| 文件大小： | 270K |
| 代理商： | A63L73321SERIES |
A63L73321 Series
PRELIMINARY (June, 1999, Version 0.1)
12
AMIC Technology, Inc.
Timing Waveforms (continued)
CLK
ADSP
ADSC
ADDRESS
A1
A2
A3
OE
D(A2)
D(A2+1)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1)
High-Z
DIN
t
AH
t
AS
t
ADSH
t
ADSS
t
ADSH
t
ADSS
t
KL
t
KH
t
KC
t
ADSH
ADSS
ADSC extends t
GW
CE
(NOTE 2)
ADV
D(A1)
D(A2+1)
D(A3+2)
DOUT
BURST READ
Single WRITE
Extended BURST WRITE
t
OEHZ
t
DH
t
DS
(NOTE 3)
(NOTE 4)
ADV suspends burst
t
ADVH
t
ADVS
t
CEH
t
CES
t
WH
t
WS
BYTE WRITE signals are ignored
for first cycle when ADSP initiates burst
t
WH
t
WS
BWE,BW1-BW4
(NOTE 5)
(NOTE 1)
Don't Care
Undefined
Write Timing
Notes: 1. D(A2) refers to output from address A2. D(A2+1) refers to output from the internal burst address immediately
following A2.
2. Timing for
CE2
and CE2 is identical to that for
CE
. As shown in the above diagram, when
CE
is LOW,
CE2
is LOW and CE2 is HIGH. When
CE
is HIGH,
CE2
is HIGH and CE2 is LOW.
3.
OE
must be HIGH before the input data setup, and held HIGH throughout the data hold period. This prevents
input/output data contention for the period prior to the time Byte Write enable inputs are sampled.
4.
ADV
must be HIGH to permit a Write to the loaded address.
5. Byte Write enables are decided by means of a Write truth table.
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