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参数资料
| 型号： | A63L73321SERIES |
| 元件分类： | 通用总线功能 |
| 英文描述： | 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output |
| 中文描述： | 128K的× 32位同步计数器高的Burst SRAM的速度和流量，通过数据输出 |
| 文件页数： | 7/17页 |
| 文件大小： | 270K |
| 代理商： | A63L73321SERIES |
A63L73321 Series
PRELIMINARY (June, 1999, Version 0.1)
6
AMIC Technology, Inc.
Notes: 1. X = "Disregard", H = Logic High, L = Logic Low.
2.
WRITE
= L means:
1) Any
BWx
(
BW1
,
BW2
,
BW3
, or
BW4
) and
BWE
are low or
2)
GW
is low.
3. All inputs except
OE
must be synchronized with setup and hold times around the rising edge (L-H) of CLK.
4. For write cycles that follow read cycles,
OE
must be HIGH before the input data request setup time and held
HIGH throughout the input data hold time.
5.
ADSP
LOW always initiates an internal Read at the L-H edge of CLK. A Write is performed by setting one or
more byte write enable signals and
BWE
LOW or
GW
LOW for the subsequent L-H edge of CLK. Refer to
the Write timing diagram for clarification.
Write Truth Table
Operation
GW
BWE
BW1
BW2
BW3
BW4
READ
H
H
X
X
X
X
READ
H
L
H
H
H
H
WRITE Byte 1
H
L
L
H
H
H
WRITE all bytes
H
L
L
L
L
L
WRITE all bytes
L
X
X
X
X
X
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相关代理商/技术参数 |
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| A63L7332E-42 | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| A63L7332E-45 | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
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