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参数资料
| 型号： | A8515GLPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 13/34页 |
| 文件大小： | 0K |
| 描述： | IC LED DVR WHT/RGB BKLGT 16TSSOP |
| 标准包装： | 8,000 |
| 拓扑： | PWM，升压（升压） |
| 输出数： | 2 |
| 内部驱动器： | 是 |
| 类型 - 主要： | 背光 |
| 类型 - 次要： | 白色 LED |
| 频率： | 600kHz ~ 2.5MHz |
| 电源电压： | 5 V ~ 40 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 供应商设备封装： | 16-TSSOP-EP |
| 包装： | 带卷 (TR) |
| 工作温度： | -40°C ~ 105°C |
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A8515
Wide Input Voltage Range, High Efficiency
Fault Tolerant LED Driver
Inrush current caused by
Soft start function
During soft start the LEDx pins are set to sink (I LEDSS ) and the
boost switch current is reduced to the I SWSS(LIM) level to limit the
inrush current generated by charging the output capacitors. When
the converter senses that there is enough voltage on the LED pins
the converter proceeds to increase the LED current to the preset
regulation current and the boost switch current limit is switched
to the I SW(LIM) level to allow the A8515 to deliver the necessary
output power to the LEDs. This is shown in figure 7.
Frequency selection
C1
C2
C3
C4
enabling the disconnect
switch (when used)
I OUT
I IN
V OUT
EN/PWM
Operation during
I SWSS(lim)
Normal operation
I SW(lim)
The switching frequency on the boost regulator is set by the resis-
tor connected to the FSET pin, and the switching frequency can
be can be anywhere from 580 kHz to 2.3 MHz. Figure 6 shows
the typical switching frequencies, in MHz, for given resistor
values, in k Ω .
If during operation a fault occurs that will increase the switch-
t
Figure 7. Startup diagram showing the input current, output voltage, and
output current; shows I OUT (ch1, 200 mA/div.), I IN (ch2, 1 A/div.), V OUT
(ch3, 20 V/div.), and EN/PWM (ch4, 5 V/div.), 1 ms/div.
V OUT
ing frequency, the FSET pin is clamped to a maximum switching
frequency of no more than 3.5 MHz. If the FSET pin is shorted
to GND the part will shut down. For more details see the Fault
Mode table later in this section.
Sync
The A8515 can also be synchronized using an external clock on
the SYNC pin. Figure 8 shows the correspondence of a sync sig-
nal and the FSET pin, and figure 9 shows the result when a sync
signal is detected: the LED current does not show any variation
C1
C2
C3
I LED
FSET
SW node
while the frequency changeover occurs. At power-up if the FSET
pin is held low, the IC will not power-up. Only when the FSET
pin is tri-stated to allow for the pin to rise, to about 1 V, or when a
sync clock is detected, will the A8515 try to power-up.
C4
t
Figure 8. Diagram showing a synchronized FSET pin and switch node;
shows V OUT (ch1, 20 V/div.), I LED (ch2, 200 mA/div.), FSET (ch3, 2 V/div.),
and SW node (ch4, 20 V/div.), 2 μ s/div.
V OUT
C1
2.1
1.9
1.7
1.5
1.3
C2
I LED
1.1
0.9
C3
2 MHz operation
FSET
1 MHz operation
0.7
0.5
SW node
10.0
12.5
15.0
17.5
20.0
22.5
25.0
30.0
32.5
35.0
Resistance for R SET (k Ω )
Figure 6. Typical Switching Frequency versus value of R FSET resistor.
C4
t
Figure 9. Transition of the SW waveform when the SYNC pulse is
detected. The A8515 switching at 2 MHz, applied SYNC pulse at 1 MHz;
shows V OUT (ch1, 20 V/div.), I LED (ch2, 200 mA/div.), FSET (ch3, 2 V/div.),
and SW node (ch4, 20 V/div.), 5 μ s/div.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13
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