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参数资料
| 型号： | A8515GLPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 22/34页 |
| 文件大小： | 0K |
| 描述： | IC LED DVR WHT/RGB BKLGT 16TSSOP |
| 标准包装： | 8,000 |
| 拓扑： | PWM，升压（升压） |
| 输出数： | 2 |
| 内部驱动器： | 是 |
| 类型 - 主要： | 背光 |
| 类型 - 次要： | 白色 LED |
| 频率： | 600kHz ~ 2.5MHz |
| 电源电压： | 5 V ~ 40 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 供应商设备封装： | 16-TSSOP-EP |
| 包装： | 带卷 (TR) |
| 工作温度： | -40°C ~ 105°C |
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A8515
Input UVLO
Wide Input Voltage Range, High Efficiency
Fault Tolerant LED Driver
able all current sources and wait until the EN/PWM signal goes
When V IN and V SENSE rise above the V UVLOrise threshold, the
A8515 is enabled. A8515 is disabled when V IN falls below the
V UVLOfall threshold for more than 50 μ s. This small delay is used
to avoid shutting down because of momentary glitches in the
input power supply. When V IN falls below 4.35 V, the IC will
shut down (see figure 30).
VDD
The VDD pin provides regulated bias supply for internal circuits.
Connect the capacitor C VDD with a value of 0.1 μ F or greater to
this pin. The internal LDO can deliver no more than 2 mA of cur-
rent with a typical V DD of about 3.5 V, enabling this pin to serve
as the pull-up voltage for the ˉF ˉAˉ ˉUˉ ˉLˉ ˉTˉ pin.
Shutdown
If the EN/PWM pin is pulled low for more than t PWML , the
device enters shutdown mode and clears all internal fault reg-
isters. As an example, at a 2 MHz clock frequency, it will take
approximately 16.3 ms to shut down the IC into the low power
mode (figure 31). When the A8515 is shut down, the IC will dis-
high to re-enable the IC. If faster shut down is required the FSET
pin can be used.
Fault protection during operation
The A8515 constantly monitors the state of the system to deter-
mine if any fault conditions occur during normal operation. The
response to a triggered fault condition is summarized in the Fault
Mode table, on the next page.
The possible fault conditions that the device can detect are: Open
LED pin, LED pin shorted to GND, shorted inductor, V OUT short
to GND, SW pin shorted to GND, ISET pin shorted to GND, and
input disconnect switch source shorted to GND.
Note the following:
? Some of the protection features might not be active during
startup, to prevent false triggering of fault conditions.
? Some of these faults will not be protected if the input
disconnect switch is not being used. An example of this is
VOUT short to ground.
GATE
C1
V IN
C2
C1
C2
I OUT
V DD
I OUT
V DD
C3
EN/PWM
C4
t
Figure 30. Shutdown showing a falling input voltage (V IN ); shows V IN
(ch1, 2 V/div.), I OUT (ch2, 200 mA/div.), V DD (ch3, 5 V/div.), and EN/PWM
(ch4, 2 V/div.), 5 ms/div.
C3
EN/PWM
C4
t
Figure 31. Shutdown using the enable function, showing the 16 ms
delay between the EN/PWM signal and when the VDD and GATE of
the disconnect switch turns off; shows GATE (ch1, 10 V/div.), I OUT (ch2,
200 mA/div.), V DD (ch3, 5 V/div.), and EN/PWM (ch4, 2 V/div.), 5 ms/div.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
22
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