参数资料
型号: A8670EESTR-T
厂商: Allegro Microsystems Inc
文件页数: 11/28页
文件大小: 0K
描述: IC REG BUCK ADJ 2A 20QFN
标准包装: 1
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 可调至 0.6V
输入电压: 7 V ~ 16 V
PWM 型: 电流模式
频率 - 开关: 200kHz ~ 1MHz
电流 - 输出: 2A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-WFQFN 裸露焊盘
包装: 标准包装
供应商设备封装: 20-QFN 裸露焊盘(4x4)
其它名称: 620-1397-6
A8670
Fixed Frequency, 2 A Synchronous Buck Regulator
With Fault Warnings and Power OK
(12)
t SS =
As mentioned in the Output Capacitor Selection section, the
effects of voltage biasing should be taken into account when
choosing the capacitor voltage rating. If ceramic capacitors are
being used, then there is generally no need to consider the effects
of ESR heating.
Soft-Start and Output Overloads
The soft-start routine controls the rate of rise of the reference
voltage, which in turn controls the FB pin, and thereby the out-
put voltage (V OUT )(see figure 1). This function minimizes the
amount of inrush current drawn from the input voltage (V IN ) and
potential voltage overshoot on the output rail (V OUT ).
A soft-start routine is initiated when the enable pin (EN) is high,
no overvoltage exists on the output, the thermal protection cir-
cuitry is not activated, and V IN is above the undervoltage thresh-
old. Immediately after EN goes high, the soft-start capacitor is
charged via an internal 10 μ A source and PWM switching action
occurs. During the Soft-Start Ramp Time (see A in figure 1), the
reference is ramped from 0 up to 0.6 V, and the output voltage
( V OUT ) tracks the reference voltage. The POK flag is held low
until the output voltage reaches 90% (typical) of the target volt-
age and a delay of 90 μ s (typical) occurs.
When an output overcurrent event occurs, the regulator imme-
diately limits the valley current at a constant level on a pulse-by
pulse basis. The output voltage will tend to fold back, depending
on how low the output impedance is. When the output voltage
Enable (EN)
0 V
Soft-Start (SS)
drops below 85% (typical) of the target voltage, the POK flag
goes low. If the overload occurs for shorter than the Hiccup
Overload Duration (<50 μ s; B in figure 1), the output will auto-
matically recover to the target level. If the overload occurs for
longer than the Hiccup Overload Duration (> 50 μ s; C in figure
1), the regulator will shut down, the soft-start capacitor will be
discharged, and (assuming no other fault conditions exist and the
enable pin is still high) the regulator will be delayed by the Hic-
cup Shutdown Duration (D in figure 1).
The Hiccup Shutdown Duration ensures that prolonged overload
conditions do not cause excessive junction temperatures to occur.
After the Hiccup Shutdown Duration has elapsed, the output
voltage is again brought up, controlled by the soft-start function.
However, if the overload condition still exists and still remains
after the Soft-Start Ramp Time has elapsed, the regulator will
shut down and the process will repeat until the fault is removed.
The Soft-Start Ramp Time, t ss , can be found from the following
formula:
C SS 0.6
10 ×10 –6
where C SS is C5 in the Typical Applications section circuit dia-
grams.
Although the A8670 is optimized for ceramic output capacitors,
large value electrolytic capacitors can be used where either spe-
cial hold-up, or power sequencing is required. Note the guidelines
for selecting large value capacitors in the Control Loop section.
0 V
A
Soft-Start Ramp Time
Target output voltage
A
Soft-Start Ramp Time
Target output voltage
Output Voltage
90% of
Target
90% of
Target
85% of
Target
0 V
Valley Current Limit
Maximum load
B
C
Maximum load
Load Current
0A
<50 μ s
Hiccup Overload
Duration
>50 μ s
Hiccup Overload
Duration
D
power OK (POK)
90 μ s
POK Delay
90 μ s
POK Delay
> 200 μ s
Hiccup Shutdown
Duration
90 μ s
POK Delay
0V
Figure 1. Operation of the soft-start function
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
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