参数资料
| 型号： | A8670EESTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 15/28页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 2A 20QFN |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 可调至 0.6V |
| 输入电压： | 7 V ~ 16 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 200kHz ~ 1MHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-WFQFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 20-QFN 裸露焊盘（4x4） |
| 其它名称： | 620-1397-6 |
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A8670
Fixed Frequency, 2 A Synchronous Buck Regulator
With Fault Warnings and Power OK
f z(EA) = (16)
f p2(EA) = (17)
R O = = 1.4 M Ω (14)
It is recommended that X5R/ X7R ceramic capacitors be used,
however, large-value capacitors such as electrolytic types can
be used. Care should be taken when selecting the value of an
electrolytic capacitor. As this capacitance is increased, the power
pole is pushed to such a low frequency that the gain can fall off
sufficiently to cause a loop instability.
If using an electrolytic capacitor, consideration should also be
given to the equivalent series resistance (ESR) value, because
this introduces a zero with the capacitance itself. It is important
to use a low-ESR type capacitor. It should be noted that capacitor
manufacturers usually quote an ESR which is a maximum at a
particular frequency (such as 100 kHz) and temperature (20°C).
The ESR does vary with frequency and temperature, plus there
are tolerance effects as well. If the zero produced by the ESR
of the output capacitor features in the control loop, it is strongly
recommended that a large tolerance be allowed. If necessary, the
high frequency pole in the error amplifier can be used to negate
the effects of this pole (see the Error Amplifier section).
Error Amplifier
The error amplifier is a transconductance amplifier. The DC
gain of the amplifier is 61dB (1122) and, with a g m value of
800 μ A / V, the effective output impedance of the amplifier can be
modeled as:
1122
800 ×10 –6
The transconductance amplifier has a high DC gain to ensure
good regulation. The gain is rolled off with a single pole posi-
tioned at a low frequency. A zero is positioned at higher frequen-
cies to cancel the effects of the main power stage pole. A second
pole can be introduced which should have minimal effect on the
loop response, but is useful for reducing the effects of switching
noise.
The zero occurs at:
1
2 × × R 4 × C 7
The high frequency pole occurs at:
1
2 × × R 4 × C 8
The potential divider formed by R5 and R6 in figure 3 effec-
tively introduces a DC offset to the loop. This can be found from:
V FB / V OUT .
Control Loop Design Approach
There are many different approaches to designing the feedback
loop. The optimum solution is to select a target phase margin
and bandwidth for optimum transient response. This typically
requires either simulation software or detailed Bode plot analysis
to generate a solution.
The particular approach described here derives a solution through
a series of basic calculations. This approach aims for a simple
–20 dB/decade roll off, from the low frequency error amplifier
pole (f p1(EA) ) to the 0 dB crossover point (f cross ). The 0 dB cross-
over point is aimed at a thirteenth of the switching frequency
(f SW ). This factor is chosen as a compromise between good band-
width and minimizing the phase lag introduced by the second
power pole, which occurs between 1 / 3 and 1 / 6 of the switching
frequency. In theory, this should introduce a phase margin of 90°,
however, in practice it will be slightly less than this, perhaps by
about 5°, due to the effects of the second power pole.
It is recommended that the error amplifier high frequency pole
should be positioned one octave below the switching frequency.
This provides some attenuation of the switching ripple whilst
having minimum impact on the closed loop response.
To achieve a –20 dB/decade roll off, the error amplifier zero is
f p1(EA) =
The low frequency pole occurs at:
1
2 × × R O × C 7
(15)
positioned to coincide with the power pole at maximum load.
Figure 5 illustrates the power stage gain, the error amplifier gain,
and then the combined overall loop response (power stage and
error amplifier).
14
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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