参数资料
| 型号： | A8670EESTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 14/28页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 2A 20QFN |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 可调至 0.6V |
| 输入电压： | 7 V ~ 16 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 200kHz ~ 1MHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-WFQFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 20-QFN 裸露焊盘（4x4） |
| 其它名称： | 620-1397-6 |
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A8670
Control Loop
Fixed Frequency, 2 A Synchronous Buck Regulator
With Fault Warnings and Power OK
From a small-signal point of view, the power inductor behaves
f p(PS) = (13)
To a first order, the small-signal loop can be modeled as shown in
figure 3. The control loop can be broken into two sections: power
stage and error amplifier.
Power Stage
The power stage includes the output filter capacitor (C OUT ),
the equivalent load (R LOAD ), and: the inner current loop, PWM
modulator, and power inductor, which together are modeled as
a transconductance amplifier with a gain of 1.3 A / V. The signal
V c , supplied to the power stage, is effectively the load current
demand signal. This signal effectively controls the valley current
through the inductor; the higher the load the larger the V c signal.
To simplify matters, we will assume this signal controls the aver-
age current through the inductor as opposed to the valley current.
The effective DC gain of the power stage, without the output
capacitor and load resistor, is 1.3 A / V, where the signal V c is
limited to the range 0.36 to 2.75 V. The DC current is converted
into V OUT as the current flows into the load resistor. The overall
DC gain of the power stage is given as V OUT / V c (see figure 4).
At full load, the V c signal would be 2 /1.3 = 1.54 V.
Power Stage
like a current source; the inductor can be ignored as far as the
bandwidth of the loop is concerned. The output capacitor inte-
grates the ripple current through the inductor, effectively forming
a single pole with the output load.
The power stage pole can be found:
1
2 × × C OUT × R LOAD
It can be seen that as the load changes, the position of the power
pole changes in the frequency domain. This may seem like an
issue in terms of where to optimize the loop, however, the change
in load also changes the gain in the power stage, thus compensat-
ing for this effect. Figure 4 illustrates how the loop response of the
power stage changes with a varying load. The position of f p1 and
G1 is one solution, f p2 and G2 is another solution, and so forth.
As the value of R LOAD increases (reducing load), the power
pole moves down in frequency and the DC gain increases.
Generally speaking this is not a problem, because even if the
pole approaches the low frequency pole produced by the error
amplifier, there is still plenty of gain in the system. In this case,
while the phase margin may be greatly reduced, even to a value
approaching 0°, because there is sufficient DC gain in the loop it
can be shown from Nyquist theory that the system is condition-
ally stable. The phase margin must be considered only at the 0 dB
V c
Amplifier
g m =
1.3 A / V
Il
C OUT
V OUT
R LOAD
crossover frequency.
G1
COMP
Pin
g m =
800 μ A / V
FB Pin
R5
R6
Gain
(dB)
G2
G3
R LOAD
increasing
V OUT
V c
C8
R4
Ro
Ref
C7
Error Amplifier
f p1 f p2
Frequency
f p3
Figure 3. 1 st order model of the small-signal control loop (see Typical
Applications section circuit diagrams for component references)
Figure 4. Power stage DC gain characteristic
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13
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