参数资料
| 型号： | A8670EESTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 5/28页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 2A 20QFN |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 可调至 0.6V |
| 输入电压： | 7 V ~ 16 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 200kHz ~ 1MHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-WFQFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 20-QFN 裸露焊盘（4x4） |
| 其它名称： | 620-1397-6 |
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A8670
Fixed Frequency, 2 A Synchronous Buck Regulator
With Fault Warnings and Power OK
Pin-out Diagram
PGND
PGND
1
2
15
14
LX
LX
VIN
BIAS
TON
3
4
5
PAD
13
12
11
LX
BOOT
FAULT
Terminal List Table
Number
1,2,20
3
4
5
6,19
7
8
9
10
11
12
13,14,
15,16
17
18
–
Name
PGND
VIN
BIAS
TON
AGND
COMP
FB
SS
POK
ˉFˉ ˉA ˉUˉˉLˉ ˉTˉ
BOOT
LX
EN
ILIM
PAD
Function
Power ground. Connect to common ground.
Power input for the control circuits and the drain of the internal high-side MOSFET. This pin must be locally
bypassed (see Typical Applications section circuit diagrams).
Internal bias decoupling capacitor. Refer to the see Typical Applications section circuit diagrams, for
recommended capacitors.
On-Time pin. The resistor connected between this pin and VIN defines the on-time of the regulator. This in
turn defines the switching frequency for a given output voltage.
Analog ground. Connect to common ground. This pin should be used as the FB resistor divider ground
reference for optimal accuracy (see Typical Applications section circuit diagrams).
Output of the error amplifier and compensation node. Connect a series R-C network from this pin to GND for
control loop regulation.
Feedback input pin of the error amplifier. Connect a resistor divider from the converter output voltage node,
VOUT, to this pin to set the converter output voltage.
Soft-start ramp pin. The capacitor connected to this pin defines the rate of rise of the output voltage and the
effective inrush current.
Open drain Power Okay (power good) output. This pin will be a logic low if any fault (as defined in table 3)
occurs, other than an overtemperature condition (T J > 140°C).
Open drain ˉFˉ ˉA ˉUˉˉLˉ ˉTˉ output. This pin will be logic low if the on-time exceeds a certain value, if the LX node is
shorted to ground, or if the thermal shutdown threshold has been reached (T J > 160°C). See table 3.
High-side gate drive supply input. This pin supplies the drive for the high-side switching MOSFET switch.
Connect a 10 nF ceramic bootstrap capacitor between BOOT and LX.
The source of the internal high-side switching MOSFET. The output inductor and BOOT capacitor should be
connected to this pin (see Typical Applications section circuit diagrams).
Enable pin. This pin is a logic input that turns the converter on or off. When EN > V ENHI , the part turns on.
Pulse-by-pulse current limit setting. Leave this pin unconnected for maximum current from the regulator, or
set this pin to GND for 50% current reduction.
Exposed pad of the package provides both electrical contact to the ground and good thermal contact to the
PCB. This pad must be soldered to the PCB for proper operation and should be connected to the ground
plane by through-hole vias. See Layout section for further details.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
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