参数资料
| 型号： | A8670EESTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 17/28页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 2A 20QFN |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 可调至 0.6V |
| 输入电压： | 7 V ~ 16 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 200kHz ~ 1MHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-WFQFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 20-QFN 裸露焊盘（4x4） |
| 其它名称： | 620-1397-6 |
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A8670
Fixed Frequency, 2 A Synchronous Buck Regulator
With Fault Warnings and Power OK
RC = (23)
2 × × 2.96 ×10 – 6 × 436.5
2 × × R LOAD × C OUT
2 × × 0.75 × 20 ×10 –6
R 4 =
2 × × C 7 × f p(PS)
2 × × 1 ×10 –9 × 10610
3a.We know that at 53.8 kHz the gain is 0 dB (1).Therefore the
constant RC can be worked out:
1
2 × × 53.8 ×10 3 × 1
= 2.96 ×10 – 6
3b. A magnitude of 52.8 dB = 436.5. The frequency at which a
gain of 436.5 is reached is:
1
f = (24)
= 123 Hz
So the overall loop response objective is shown in figure 6.
4. Select the RC components.
4a. The error amplifier pole (f p1(EA) ) occurs at 123 Hz. Therefore,
C7 can be found:
1
f p(PS) = (26)
1
=
= 10 610 Hz
4c. The error amplifier zero (f z(EA) ) also occurs at 10.610 kHz to
cancel the effects of the power pole. Therefore, as C7 is known,
R4 can be found:
1
(27)
1
=
= 15 k Ω
C 7 =
1
2 × × R O × f p1(EA)
(25)
4d. The error amplifier high frequency pole (f p2(EA) ) is set an
octave below the switching frequency. Therefore, C8 can be
2 × × 1.4 ×10 6 × 123
2 × × R 4 × ( f SW /2)
3 × (700 ×10 3 / 2)
=
1
=
= 1 nF
4b. The power pole (f p(PS) ) can be found, because the output
capacitor (C OUT ) and maximum load (R LOAD ) are known:
found:
C 8 =
2 × × 15 ×10
= 30 pF
1
1
(28)
4e. Using the above compensation component selection tech-
nique, table 4 provides preferred component values for a given
output voltage, 2 A output, at target switching frequencies of
52.8
f p1(EA)
f p(PS), f z(EA)
500 kHz, 700 kHz, and 1 MHz.
Table 4. Recommended R4 and C7 Values
Switching Frequency, f SW
500 kHz
700 kHz
1 MHz
–2
0d
B/
de
ca
de
V OUT
(V)
5.0
R4
(k Ω )
33
C7
(nF)
1.5
V OUT
(V)
5.0
R4
(k Ω )
51
C7
(nF)
1.0
V OUT
(V)
5.0
R4
(k Ω )
68
C7
(nF)
0.68
3.3
22
1.5
3.3
33
1.0
3.3
51
0.68
f cross
2.5
1.8
18
12
1.5
1.5
2.5
1.8
24
18
1.0
1.0
2.5
1.8
39
27
0.68
0.68
0.123
Frequency (kHz)
53.8
1.5
10
1.5
1.5
15
1.0
1.5
22
0.68
1.2
8.2
1.5
1.2
12
1.0
1.2
18
0.68
Figure 6. Design example objective: overall control loop response (power
stage and error amplifier)
1.0
0.8
0.6
6.8
4.7
3.9
1.5
1.5
1.5
1.0
0.8
0.6
10
8.2
5.6
1.0
1.0
1.0
1.0
0.8
0.6
15
12
8.2
0.68
0.68
0.68
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
16
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