参数资料
型号: ACT-7000ASC-225F24Q
元件分类: 微控制器/微处理器
英文描述: 64-BIT, 225 MHz, RISC PROCESSOR, CQFP208
封装: 1.120 X 1.120 INCH, INVERTED, CERAMIC, QFP-208
文件页数: 16/26页
文件大小: 231K
代理商: ACT-7000ASC-225F24Q
23
SCD7000A Rev C 9/9/09
Aeroflex Plainview
For additional Detail Information regarding the operation of the PMC-Sierra see the latest PMC-Sierra datasheet for
the RM7000A 64-Bit Superscalar Microprocessor with On-Chip Secondary Cache (doc. # PMC-2002227), Issue No. 5:
August, 2002
JTAG interface:
JTDI
Input
JTAG data in
JTAG serial data in.
JTCK
Input
JTAG clock input
JTAG serial clock input.
JTDO
Output
JTAG data out
JTAG serial data out.
JTMS
Input
JTAG command
JTAG command signal, signals that the incoming serial data is command data.
Initialization Interface:
BigEndian
Input
Big Endian / Little Endian Control
Allows the system to change the processor addressing mode without rewriting
the mode ROM.
VccOK
Input
Vcc is OK
When asserted, this signal indicates to the ACT-7000ASC that the VCCINT power
supply has been above the recommended value for more than 100 milliseconds
and will remain stable. The assertion of VccOK initiates the reading of the
boot-time mode control serial stream.
ColdReset*
Input
Cold Reset
This signal must be asserted for a power on reset or a cold reset. ColdReset
must be de-asserted synchronously with SysClock.
Reset*
Input
Reset
This signal must be asserted for any reset sequence. It may be asserted
synchronously or asynchronously for a cold reset, or synchronously to initiate a
warm reset. Reset must be de-asserted synchronously with SysClock.
ModeClock
Output
Boot Mode Clock
Serial boot-mode data clock output at the system clock frequency divided by two
hundred and fifty six.
ModeIn
Input
Boot Mode Data In
Serial boot-mode data input.
Pin Descriptions (cont)
The following is a list of control, data, clock, interrupt, and miscellaneous pins of the ACT 7000ASC.
Pin Name
Type
Description
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