- 您现在的位置：买卖IC网 > PDF目录298813 > ACT-7000ASC-225F24Q 64-BIT, 225 MHz, RISC PROCESSOR, CQFP208 PDF资料下载
参数资料
| 型号： | ACT-7000ASC-225F24Q |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 225 MHz, RISC PROCESSOR, CQFP208 |
| 封装： | 1.120 X 1.120 INCH, INVERTED, CERAMIC, QFP-208 |
| 文件页数： | 3/26页 |
| 文件大小： | 231K |
| 代理商： | ACT-7000ASC-225F24Q |
11
SCD7000A Rev C 9/9/09
Aeroflex Plainview
Cache Locking
The ACT 7000ASC allows critical code or data
fragments to be locked into the primary and secondary
caches. The user has complete control over what locking is
performed with cache line granularity. For instruction and
data fragments in the primaries, locking is accomplished by
setting either or both of the cache lock enable bits in the
CP0 ECC register, specifying the set via a field in the CP0
ECC register, and then executing either a load instruction
or a Fill_I cache operation for data or instructions
respectively. Only two sets are lockable within each cache:
set A and set B. Locking within the secondary works
identically to the primaries using a separate secondary lock
enable bit and the same set selection field. As with the
primaries, only two sets are lockable: sets A and B. Table 7
summarizes the cache locking capabilities.
Cache Management
To improve the performance of critical data movement
operations
in
the
embedded
environment,
the
ACT 7000ASC significantly improves the speed of
operation of certain critical cache management operations
as compared with the R5000 and R4000 families. In
particular, the speed of the Hit-Write-back-Invalidate and
Hit-Invalidate cache operations has been improved in some
cases by an order of magnitude over that of the earlier
families. Table 8 compares the ACT 7000ASC with the
R4000 and R5000 processors.
For the Hit-Dirty case of Hit-Writeback-Invalidate, if the
writeback buffer is full from some previous cache eviction
then n is the number of cycles required to empty the
write-back buffer. If the buffer is empty then n is zero.
The penalty value is the number of processor cycles
beyond the one cycle required to issue the instruction that
is required to implement the operation.
Primary Write Buffer
Writes to secondary cache or external memory, whether
cache miss write-backs or stores to uncached or
write-through addresses, use the integrated primary write
buffer. The write buffer holds up to four 64-bit address and
data pairs. The entire buffer is used for a data cache
write-back and allows the processor to proceed in parallel
with memory update. For uncached and write-through
stores, the write buffer significantly increases performance
by decoupling the SysAD bus transfers from the instruction
execution stream.
System Interface
The ACT 7000ASC provides a high-performance 64-bit
system interface which is compatible with the RM5200
Family and R5000. Unlike the R4000 and R5000 family
processors which provide only an integral multiplication
Index
vAddr 11..0
pAddr 15..0
Tag
pAddr 35..12
pAddr 35..16
Write policy
n.a.
write-back, write-through
block write-back, bypass
read policy
n.a.
non-blocking (2 outstanding) non-blocking (data only, 2
outstanding)
read order
critical word first
write order
NA
sequential
miss restart following:
complete line
first double (if waiting for
data)
n.a.
Parity
per word
per byte
per doubleword
Table 6 – Cache Attributes (cont)
Attribute
Instruction
Data
Secondary
Table 7 – Cache Locking Control
Cache
Lock
Enable
Set Select
Activate
Primary I
ECC[27]
ECC[28]=
0→A
ECC[28]=
1→B
Fill_I
Primary D
ECC[26]
ECC[28]=
0→A
ECC[28]=
1→B
Load/Store
Secondary
ECC[25]
ECC[28]=
0→A
ECC[28]=
1→B
Fill_I or
Load/Store
Table 8 – Penalty Cycle
Operation
Condition
Penalty
ACT 7000ASC R4000/R5000
Hit-Writeback-
Invalidate
Miss
0
7
Hit-Clean
3
12
Hit-Dirty
3+n
14+n
Hit-Invalidate
Miss
0
7
Hit
2
9
相关PDF资料 |
PDF描述 |
|---|---|
| ACT-7000ASC-300F17I | 64-BIT, 300 MHz, RISC PROCESSOR, CQFP208 |
| ACT4445 | DATACOM, MIL-STD-1553 DATA BUS TRANSCEIVER, BCC64 |
| ACTS04KMSR-02 | ACT SERIES, HEX 1-INPUT INVERT GATE, CDFP14 |
| ACTS04DMSR-02 | ACT SERIES, HEX 1-INPUT INVERT GATE, CDIP14 |
| ACTS08DMSR | ACT SERIES, QUAD 2-INPUT AND GATE, CDIP14 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ACT7000SC | 制造商:AEROFLEX 制造商全称:AEROFLEX 功能描述:ACT 7000SC 64-Bit Superscaler Microprocessor |
| ACT-7000SC-150F17C | 制造商:AEROFLEX 制造商全称:AEROFLEX 功能描述:ACT 7000SC 64-Bit Superscaler Microprocessor |
| ACT-7000SC-150F17I | 制造商:AEROFLEX 制造商全称:AEROFLEX 功能描述:ACT 7000SC 64-Bit Superscaler Microprocessor |
| ACT-7000SC-150F17M | 制造商:AEROFLEX 制造商全称:AEROFLEX 功能描述:ACT 7000SC 64-Bit Superscaler Microprocessor |
| ACT-7000SC-150F17Q | 制造商:AEROFLEX 制造商全称:AEROFLEX 功能描述:ACT 7000SC 64-Bit Superscaler Microprocessor |
发布紧急采购，3分钟左右您将得到回复。