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参数资料
| 型号： | ACT-7000ASC-225F24Q |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 225 MHz, RISC PROCESSOR, CQFP208 |
| 封装： | 1.120 X 1.120 INCH, INVERTED, CERAMIC, QFP-208 |
| 文件页数： | 2/26页 |
| 文件大小： | 231K |
| 代理商： | ACT-7000ASC-225F24Q |
10
SCD7000A Rev C 9/9/09
Aeroflex Plainview
leaving the write-back bit of the cache line
unchanged; no writes will occur into the secondary.
If the cache lookup misses, then only main memory
is written.
5. Write-back with secondary bypass. Loads and
instruction fetches first search the primary cache,
reading from memory only if the desired data is not
resident; the secondary is not searched. On data store
operations, the primary cache is first searched to
determine if the target address is resident. If it is
resident, the cache contents are updated, and the
cache line marked for later write-back. If the cache
lookup misses, the target line is first brought into the
cache and then the write is performed as above.
Associated with the Data Cache is the store buffer. When
the ACT 7000ASC executes a STORE instruction, this
single-entry buffer gets written with the store data while the
tag comparison is performed. If the tag matches, then the
data is written into the Data Cache in the next cycle that the
Data Cache is not accessed (the next non-load cycle). The
store buffer allows the ACT 7000ASC to execute a store
every processor cycle and to perform back-to-back stores
without penalty. In the event of a store immediately
followed by a load to the same address, a combined merge
and cache write will occur such that no penalty is incurred.
Secondary Cache
The ACT 7000ASC has an integrated 256KB, four-way
set associative, block write-back secondary cache. The
secondary has the same line size as the primaries, 32 bytes,
is logically 64-bits wide matching the system interface and
primary widths, and is protected with doubleword parity.
The secondary tag array holds a 20-bit physical address, 2
housekeeping bits, a three bit cache state field, and two
parity bits.
By integrating a secondary cache, the ACT 7000ASC is
able to dramatically decrease the latency of a primary cache
miss without dramatically increasing the number of pins
and the amount of power required by the processor. From a
technology point of view, integrating a secondary cache
maximally leverages CMOS semiconductor technology by
using silicon to build the structures that are most amenable
to silicon technology; silicon is being used to build very
dense, low power memory arrays rather than large power
hungry I/O buffers.
Further benefits of an integrated secondary are flexibility
in the cache organization and management policies that are
not practical with an external cache. Two previously
mentioned examples are the 4-way associativity and
write-back cache protocol.
A third management policy for which integration affords
flexibility is cache hierarchy management. With multiple
levels of cache, it is necessary to specify a policy for
dealing with cases where two cache lines at level n of the
hierarchy would, if possible, be sharing an entry in level
n+1 of the hierarchy. The policy followed by the
ACT 7000ASC is motivated by the desire to get maximum
cache utility and results in the ACT 7000ASC allowing
entries in the primaries which do not necessarily have a
corresponding entry in the secondary; the ACT 7000ASC
does not force the primaries to be a subset of the secondary.
For example, if primary cache line A is being filled and a
cache line already exists in the secondary for primary cache
line B at the location where primary A’s line would reside
then that secondary entry will be replaced by an entry
corresponding to primary cache line A and no action will
occur in the primary for cache line B. This operation will
create the aforementioned scenario where the primary
cache line which initially had a corresponding secondary
entry will no longer have such an entry. Such a primary line
is called an orphan. In general, cache lines at level n+1 of
the hierarchy are called parents of level n’s children.
Another
ACT 7000ASC
cache
management
optimization occurs for the case of a secondary cache line
replacement where the secondary line is dirty and has a
corresponding dirty line in the primary. In this case, since
it is permissible to leave the dirty line in the primary, it is
not necessary to write the secondary line back to main
memory. Taking this scenario one step further, a final
optimization occurs when the aforementioned dirty
primary line is replaced by another line and must be written
back, in this case, it will be written directly to memory
bypassing the secondary cache.
Secondary Caching Protocols
Unlike the primary data cache, the secondary cache
supports only uncached and block write-back. As noted
earlier,
cache
lines
managed
with
either
of
the
write-through protocols will not be placed in the secondary
cache. A new caching attribute, write-back with secondary
bypass, allows the secondary to be bypassed entirely.
When this attribute is selected, the secondarywill not be
filled on load misses and will not be written on dirty
write-backs from the primary.
Table 6 – Cache Attributes
Attribute
Instruction
Data
Secondary
Size
16KB
256KB
Associativity
4-way
Replacement Algorithm.
cyclic
Line size
32 byte
相关PDF资料 |
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| ACT4445 | DATACOM, MIL-STD-1553 DATA BUS TRANSCEIVER, BCC64 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ACT7000SC | 制造商:AEROFLEX 制造商全称:AEROFLEX 功能描述:ACT 7000SC 64-Bit Superscaler Microprocessor |
| ACT-7000SC-150F17C | 制造商:AEROFLEX 制造商全称:AEROFLEX 功能描述:ACT 7000SC 64-Bit Superscaler Microprocessor |
| ACT-7000SC-150F17I | 制造商:AEROFLEX 制造商全称:AEROFLEX 功能描述:ACT 7000SC 64-Bit Superscaler Microprocessor |
| ACT-7000SC-150F17M | 制造商:AEROFLEX 制造商全称:AEROFLEX 功能描述:ACT 7000SC 64-Bit Superscaler Microprocessor |
| ACT-7000SC-150F17Q | 制造商:AEROFLEX 制造商全称:AEROFLEX 功能描述:ACT 7000SC 64-Bit Superscaler Microprocessor |
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