参数资料
| 型号： | AD1877JRZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 1/20页 |
| 文件大小： | 0K |
| 描述： | IC ADC STEREO 16BIT 28-SOIC |
| 标准包装： | 1,000 |
| 位数： | 16 |
| 采样率（每秒）： | 45k |
| 数据接口： | 串行 |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 315mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC W |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个单端，单极 |
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
L
RCK
WCLK
BCLK
DGND1
DVDD1
RDEDGE
S/
M
384/
256
AVDD
VINL
CAPL1
CAPL2
AGNDL
VREFL
CLKIN
TAG
SOUT
DVDD2
RESET
MSBDLY
R
LJUST
AGND
VINR
CAPR1
CAPR2
AGNDR
VREFR
SERIAL OUTPUT
INTERFACE
THREE-STAGE FIR
DECIMATION
FILTER
DGND2
THREE-STAGE FIR
DECIMATION
FILTER
CLOCK
DIVIDER
VOLTAGE
REFERENCE
D
A
C
D
A
C
D
A
C
D
A
C
SINGLE TO
DIFFERENTIAL INPUT
CONVERTER
SINGLE TO
DIFFERENTIAL INPUT
CONVERTER
AD1877
REV. A
I
a
Single-Supply
16-Bit
Stereo ADC
FEATURES
Single 5 V Power Supply
Single-Ended Dual-Channel Analog Inputs
92 dB (Typ) Dynamic Range
90 dB (Typ) S/(THD+N)
0.006 dB Decimator Passband Ripple
Fourth-Order, 64-Times Oversampling
Modulator
Three-Stage, Linear-Phase Decimator
256
FS or 384
FS Input Clock
Less than 100
W (Typ) Power-Down Mode
Input Overrange Indication
On-Chip Voltage Reference
Flexible Serial Output Interface
28-Lead SOIC Package
APPLICATIONS
Consumer Digital Audio Receivers
Digital Audio Recorders, Including Portables
CD-R, DCC, MD and DAT
Multimedia and Consumer Electronic Equipment
Sampling Music Synthesizers
Digital Karaoke Systems
AD1877
one-bit comparator’s quantization noise out of the audio pass-
band. The high order of the modulator randomizes the modulator
output, reducing idle tones in the AD1877 to very low levels.
Because its modulator is single-bit, AD1877 is inherently
monotonic and has no mechanism for producing differential
linearity errors.
The input section of the AD1877 uses autocalibration to correct
any dc offset voltage present in the circuit, provided that the inputs
are ac coupled. The single-ended dc input voltage can swing
between 0.7 V and 3.8 V typically. The AD1877 antialias input
circuit requires four external 470 pF NPO ceramic chip filter
capacitors, two for each channel. No active electronics are
needed. Decoupling capacitors for the supply and reference pins
are also required.
The dual digital decimation filters are triple-stage, finite impulse
response filters for effectively removing the modulator’s high
frequency quantization noise and reducing the 64
× FS single-bit
output data rate to an FS word rate. They provide linear phase
and a narrow transition band that properly digitizes 20 kHz signals
at a 44.1 kHz sampling frequency. Passband ripple is less than
0.006 dB, and stopband attenuation exceeds 90 dB.
(Continued on Page 6)
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2000
PRODUCT OVERVIEW
The AD1877 is a stereo, 16-bit oversampling ADC based on
Sigma Delta (
∑) technology intended primarily for digital
audio bandwidth applications requiring a single 5 V power supply.
Each single-ended channel consists of a fourth-order one-bit
noise shaping modulator and a digital decimation filter. An on-
chip voltage reference, stable over temperature and time, defines
the full-scale range for both channels. Digital output data from
both channels are time-multiplexed to a single, flexible serial
interface. The AD1877 accepts a 256
× FS or a 384 × FS input
clock (FS is the sampling frequency) and operates in both serial
port “master” and “slave” modes. In slave mode, all clocks must
be externally derived from a common source.
Input signals are sampled at 64
× FS onto internally buffered
switched-capacitors, eliminating external sample-and-hold ampli-
fiers and minimizing the requirements for antialias filtering at the
input. With simplified antialiasing, linear phase can be preserved
across the passband. The on-chip single-ended to differential signal
converters save the board designer from having to provide them
externally. The AD1877’s internal differential architecture provides
increased dynamic range and excellent power supply rejection
characteristics. The AD1877’s proprietary fourth-order differen-
tial switched-capacitor
∑ modulator architecture shapes the
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