参数资料
型号: AD1877JRZ-RL
厂商: Analog Devices Inc
文件页数: 8/20页
文件大小: 0K
描述: IC ADC STEREO 16BIT 28-SOIC
标准包装: 1,000
位数: 16
采样率(每秒): 45k
数据接口: 串行
转换器数目: 2
功率耗散(最大): 315mW
电压电源: 模拟和数字
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
供应商设备封装: 28-SOIC W
包装: 带卷 (TR)
输入数目和类型: 2 个单端,单极
AD1877
REV. A
–16–
BCLK
RDEDGE = LO
BCLK
RDEDGE = HI
31
32
1
2
3
4
16
SOUT
OUTPUT
WCLK
OUTPUT
TAG
OUTPUT
19
20
21
32
1
2
INPUT
HI
517
18
LSB
LEFT TAG
MSB
LSB
RIGHT TAG
LEFT TAG
LSB
MSB-14
LSB
PREVIOUS DATA
MSB-1 MSB-2 MSB-3
LEFT DATA
MSB-4
MSB-3 MSB-4
LSB
MSB-1 MSB-2
RIGHT DATA
LSB
MSB-1
LEFT DATA
L
RCK
INPUT
MSB
Figure 15. Serial Data Output Timing: Slave Mode, Left-Justified with No MSB Delay,
32-Bit Frame Mode, S/
M = Hl, RLJUST = LO, MSBDLY = Hl
BCLK
RDEDGE = LO
BCLK
RDEDGE = HI
32
1
2
3
4
5
17
SOUT
OUTPUT
TAG
OUTPUT
20
21
22
1
2
3
INPUT
WCLK
OUTPUT
HI
618
19
MSB
LEFT TAG
MSB
LSB
RIGHT TAG
MSB-14
LSB
PREVIOUS DATA
MSB-1 MSB-2 MSB-3
LEFT DATA
MSB-4
MSB-3 MSB-4
LSB
MSB-1 MSB-2
RIGHT DATA
LSB
MSB-1
LEFT DATA
MSB
LEFT TAG
MSB
RIGHT TAG
L
RCK
INPUT
MSB
LSB
MSB
LSB
Figure 16. Serial Data Output Timing: Slave Mode, I 2S-Justified, 32-Bit Frame Mode,
S/
M = Hl, RLJUST= LO, MSBDLY = LO
BCLK OUTPUT (64 x FS)
RDEDGE = LO
CLKIN
INPUT
BCLK OUTPUT (64 x FS)
RDEDGE = HI
WCLK
OUTPUT
DATA & TAG
OUTPUTS
XMIT
tDLYCKB
tBPWL
tBPWH
tBPWL
tBPWH
tDLYBLR
tDLYDT
tDLYBWR
tDLYBWF
L
RCK
OUTPUT
Figure 17. Master Mode Clock Timing
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