参数资料
| 型号： | AD1877JRZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/20页 |
| 文件大小： | 0K |
| 描述： | IC ADC STEREO 16BIT 28-SOIC |
| 标准包装： | 1,000 |
| 位数： | 16 |
| 采样率（每秒）： | 45k |
| 数据接口： | 串行 |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 315mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC W |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个单端，单极 |
DIGITAL I/O
Min
Typ
Max
Unit
Input Voltage HI (VIH)
2.4
V
Input Voltage LO (VIL)
0.8
V
Input Leakage (IIH @ VIH = 5 V)
10
A
Input Leakage (IIL @ VIL = 0 V)
10
A
Output Voltage HI (VOH @ IOH = –2 mA)
2.4
V
Output Voltage LO (VOL @ IOL = 2 mA)
0.4
V
Input Capacitance
15
pF
DIGITAL TIMING (Guaranteed over 0
°C to 70°C, DV
DD = AVDD = 5 V
± 5%. Refer to Figures 17–19.)
Min
Typ
Max
Unit
tCLKIN
CLKIN Period
48
81
780
ns
FCLKIN
CLKIN Frequency (1/tCLKIN)
1.28
12.288
20.48
MHz
tCPWL
CLKIN LO Pulsewidth
15
ns
tCPWH
CLKIN HI Pulsewidth
15
ns
tRPWL
RESET LO Pulsewidth
50
ns
tBPWL
BCLK LO Pulsewidth
15
ns
tBPWH
BCLK HI Pulsewidth
15
ns
tDLYCKB
CLKIN Rise to BCLK Xmit (Master Mode)
15
ns
tDLYBLR
BCLK Xmit to LRCK Transition (Master Mode)
15
ns
tDLYBWR
BCLK Xmit to WCLK Rise
10
ns
tDLYBWF
BCLK Xmit to WCLK Fall
10
ns
tDLYDT
BCLK Xmit to Data/Tag Valid (Master Mode)
10
ns
tSETLRBS
LRCK Setup to BCLK Sample (Slave Mode)
10
ns
tDLYLRDT
LRCK Transition to Data/TAG Valid (Slave Mode)
No MSB Delay Mode (for MSB Only)
40
ns
tSETWBS
WCLK Setup to BCLK Sample (Slave Mode)
Data Position Controlled by WCLK Input Mode
10
ns
tDLYBDT
BCLK Xmit to DATA/TAG Valid (Slave Mode)
All Bits Except MSB in No MSB Delay Mode
All Bits in MSB Delay Mode
10
ns
POWER
Min
Typ
Max
Unit
Supplies
Voltage, Analog and Digital
4.75
5
5.25
V
Analog Current
35
43
mA
Analog Current—Power Down (CLKIN Running)
6
26
A
Digital Current
16
20
mA
Digital Current—Power Down (CLKIN Running)
13
39
A
Dissipation
Operation—Both Supplies
255
315
mW
Operation—Analog Supply
175
215
mW
Operation—Digital Supply
80
100
mW
Power Down—Both Supplies (CLKIN Running)
95
325
W
Power Down—Both Supplies (CLKIN Not Running)
5
W
Power Supply Rejection (See TPC 5)
1 kHz 300 mV p-p Signal at Analog Supply Pins
76
dB
20 kHz 300 mV p-p Signal at Analog Supply Pins
71
dB
Stopband (
≥0.55 × FS)—any 300 mV p-p Signal
80
dB
AD1877
REV. A
–3–
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