参数资料
型号: AD1877JRZ-RL
厂商: Analog Devices Inc
文件页数: 12/20页
文件大小: 0K
描述: IC ADC STEREO 16BIT 28-SOIC
标准包装: 1,000
位数: 16
采样率(每秒): 45k
数据接口: 串行
转换器数目: 2
功率耗散(最大): 315mW
电压电源: 模拟和数字
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
供应商设备封装: 28-SOIC W
包装: 带卷 (TR)
输入数目和类型: 2 个单端,单极
AD1877–SPECIFICATIONS
REV. A
–2–
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages
5.0
V
Ambient Temperature
25
°C
Input Clock (FCLKIN) [256
× FS]
12.288
MHz
Input Signal
991.768
Hz
–0.5
dB Full Scale
Measurement Bandwidth
23.2 Hz to 19.998 kHz
Load Capacitance on Digital Outputs
50
pF
Input Voltage HI (VIH)
2.4
V
Input Voltage LO (VIL)
0.8
V
Master Mode, Data I
2S-Justified (Refer to Figure 14).
Device Under Test (DUT) bypassed and decoupled as shown in Figure 3.
DUT is antialiased and ac coupled as shown in Figure 2. DUT is calibrated.
Values in bold typeface are tested, all others are guaranteed but not tested.
ANALOG PERFORMANCE
Min
Typ
Max
Unit
Resolution
16
Bits
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
Without A-Weight Filter
87
92
dB
With A-Weight Filter
90
94
dB
Signal to (THD + Noise)
86.5
90
dB
Signal to THD
92
94
dB
Analog Inputs
Single-Ended Input Range (
± Full Scale)*
VREF – 1.55
VREF
VREF + 1.55
V
Input Impedance at Each Input Pin
32
k
VREF
2.05
2.25
2.55
V
DC Accuracy
Gain Error
±0.5
2.5
%
Interchannel Gain Mismatch
0.01
dB
Gain Drift
115
ppm/
°C
Midscale Offset Error (After Calibration)
±3
20
LSBs
Midscale Drift
15
ppm/
°C
Crosstalk (EIAJ Method)
–90
–99
dB
*VIN p-p = VREF
× 1.333.
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