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参数资料
| 型号： | AD5263BRUZ50-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/28页 |
| 文件大小： | 0K |
| 描述： | IC POT DGTL 50K 256POS 24TSSOP |
| 标准包装： | 1,000 |
| 接片： | 256 |
| 电阻（欧姆）： | 50k |
| 电路数： | 4 |
| 温度系数： | 标准值 30 ppm/°C |
| 存储器类型： | 易失 |
| 接口： | I²C，SPI（芯片选择，设备位址） |
| 电源电压： | 2.7 V ~ 5.5 V，5 V ~ 15 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 带卷 (TR) |
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AD5263
Data Sheet
Rev. F | Page 20 of 28
3. In read mode, the data byte follows immediately after the
acknowledgment of the slave address byte. Data is transmitted
over the serial bus in sequences of nine clock pulses (a slight
difference with the write mode, where there are eight data
bits followed by an acknowledge bit). Similarly, the transitions
on the SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see Figure 44).
Note that the channel of interest is the one that was
previously selected in write mode. In cases where users
need to read the RDAC values of both channels, they must
program the first channel in write mode and then change
to read mode to read the first channel value. After that,
they must change back to write mode with the second channel
selected and read the second channel value in read mode
again. It is not necessary for users to issue the Frame 3 data
byte in the write mode for subsequent readback operation.
Refer to Figure 44 for the programming format.
4. After all data bits have been read or written, a stop condition is
established by the master. A stop condition is defined as a
low-to-high transition on the SDA line while SCL is high.
In write mode, the master pulls the SDA line high during the
tenth clock pulse to establish a stop condition (see Figure 43).
In read mode, the master issues a no acknowledge for the
ninth clock pulse (that is, the SDA line remains high). The
master then brings the SDA line low before the tenth clock
pulse, which goes high to establish a stop condition (see
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and instructing
the part only once. For example, after the RDAC has acknowledged
its slave address and instruction bytes in the write mode, the
RDAC output updates on each successive byte. If different
instructions are needed, the write/read mode has to start again
with a new slave address, instruction, and data byte. Similarly, a
repeated read function of the RDAC is also allowed.
ADDITIONAL PROGRAMMABLE LOGIC OUTPUT
The AD5263 features additional programmable logic outputs, O1
and O2, which can be used to drive a digital load, analog switches,
and logic gates. O1 and O2 default to Logic 0. The voltage level can
swing from GND to VL. The logic states of O1 and O2 can be
programmed in Frame 2 under write mode (see Figure 43). These
logic outputs have adequate current driving capability to
sink/source milliamperes of load.
Users can also activate O1 and O2 in three different ways without
affecting the wiper settings. They may do the following:
Start, slave address byte, acknowledge, instruction byte
with O1 and O2 specified, acknowledge, Stop.
Complete the write cycle with stop, then start, slave address
byte, acknowledge, instruction byte with O1 and O2
specified, acknowledge, stop.
Do not complete the write cycle by not issuing the stop,
then start, slave address byte, acknowledge, instruction
byte with O1 and O2 specified, acknowledge, stop.
SELF-CONTAINED SHUTDOWN FUNCTION
Shutdown can be activated by strobing the SHDN pin or
programming the SD bit in the write mode instruction byte. In
addition, shutdown can even be implemented with the device’s
digital output, as shown in Figure 48. In this configuration, the
device is shut down during power-up, but users are allowed to
program the device. Thus, when O1 is programmed high, the
device exits from the shutdown mode and responds to the new
setting. This self-contained shutdown function allows absolute
shutdown during power-up, which is crucial in hazardous
environments, without adding extra components.
03142-
047
RPULL-DOWN
SCL
O1
SHDN
SDA
AD5263
Figure 48. Shutdown by Internal Logic Output
If the shutdown function is enabled by using the SD bit, see the I2C
show the sequences that can place any channel in an undesirable
shutdown state.
Table 8. Direct Sequence
Command Sequence
RDAC Shutdown
Write RDAC 1, SHDN RDAC 2
RDAC1 and RDAC2
Write RDAC 2, SHDN RDAC 1
RDAC1 and RDAC2
Write RDAC 3, SHDN RDAC 4
RDAC3 and RDAC4
Write RDAC 4, SHDN RDAC 3
RDAC3 and RDAC4
To overcome the issue, employ the following sequence, as an
example for the first case:
Start, slave address byte, acknowledge, instruction byte
(write RDAC1), acknowledge, data byte, acknowledge, stop.
Start, slave address byte, acknowledge, instruction byte
(write RDAC1), acknowledge, stop.
Start, slave address byte, acknowledge, instruction byte
(SHDN RDAC2), acknowledge, data byte, acknowledge, stop.
Table 9. Indirect Sequence
Command Sequence
RDAC Shutdown
Write RDAC 1, SHDN RDAC 1, SHDN RDAC 4
RDAC1, RDAC3,
and RDAC4
Write RDAC 3, SHDN RDAC 3, SHDN RDAC 2
RDAC1, RDAC2,
and RDAC3
To overcome this issue, swap the SHDN order command, for
example, write RDAC 1, SHDN RDAC 4, and then SHDN
RDAC 1.
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