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参数资料
| 型号： | AD5263BRUZ50-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/28页 |
| 文件大小： | 0K |
| 描述： | IC POT DGTL 50K 256POS 24TSSOP |
| 标准包装： | 1,000 |
| 接片： | 256 |
| 电阻（欧姆）： | 50k |
| 电路数： | 4 |
| 温度系数： | 标准值 30 ppm/°C |
| 存储器类型： | 易失 |
| 接口： | I²C，SPI（芯片选择，设备位址） |
| 电源电压： | 2.7 V ~ 5.5 V，5 V ~ 15 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 带卷 (TR) |
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AD5263
Data Sheet
Rev. F | Page 22 of 28
VLOGIC POWER SUPPLY
The AD5263 is capable of operating at high voltages beyond the
internal logic levels, which are limited to operation at 5 V. As a
result, VL always needs to be tied to a separate 2.7 V to 5.5 V source
to ensure proper digital signal levels. Logic levels must be limited to
VL, regardless of VDD. In addition, VL should always be less than
or equal to VDD.
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum-lead length
layout design. The leads to the input should be as direct as possible
with a minimum conductor length. Ground paths should have
low resistance and low inductance.
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with 0.01 F to 0.1 F ceramic
disc or chip capacitors. Low ESR 1 F to 10 F tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance and low frequency ripple
(see Figure 55). Notice the digital ground should also be joined
remotely to the analog ground at one point to minimize the
ground bounce.
03142-
055
GND
VSS
VDD
AD5263
VSS
VDD
C1
0.1F
C2
0.1F
C3
10F
C4
10F
+
Figure 55. Power Supply Bypassing
RDAC CIRCUIT SIMULATION MODEL
The internal parasitic capacitances and the external capacitive loads
dominate the ac characteristics of the RDACs. Configured as a
potentiometer divider, the –3 dB bandwidth of the AD5263 (20 k
resistor) measures 300 kHz at half scale. Figure 22 provides the
large signal BODE plot characteristics of the three available
resistor versions: 20 k, 50 k, and 200 k. A parasitic simulation
model is shown in Figure 56. The following code provides a
macro model net list for the 20 k RDAC.
03142-
069
20k
CA
W
25pF
RDAC
A
B
CB
CW
25pF
55pF
Figure 56. RDAC Circuit Simulation Model for RDAC = 20 k
Listing 1. Macro Model Net List for RDAC
.PARAM D=256, RDAC=20E3
*
.SUBCKT DPOT (A,W,B)
*
CA
A
0
25E-12
RWA
A
W
{(1-D/256)*RDAC+60}
CW
W
0
55E-12
RWB
W
B
{D/256*RDAC+60}
CB
B
0
25E-12
*
.ENDS DPOT
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相关代理商/技术参数 |
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|---|---|
| AD5263EVAL | 制造商:Analog Devices 功能描述:Evaluation Board For Digital Potentiometer, Quad, 15V, 256-Position, Digital Potentiometer 制造商:Analog Devices 功能描述:AD5263 EVAL BOARD - Bulk |
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| AD5266 | 制造商:ESMT 制造商全称:Elite Semiconductor Memory Technology Inc. 功能描述:16V STEREO CLASS-D AUDIO POWER AMPLIFIER with STEREO HEADPHONE |
| AD526A | 制造商:AD 制造商全称:Analog Devices 功能描述:Software Programmable Gain Amplifier |
| AD526AD | 功能描述:IC AMP PGA 10MA 16CDIP RoHS:否 类别:集成电路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 标准包装:2,500 系列:Excalibur™ 放大器类型:J-FET 电路数:1 输出类型:- 转换速率:45 V/µs 增益带宽积:10MHz -3db带宽:- 电流 - 输入偏压:20pA 电压 - 输入偏移:490µV 电流 - 电源:1.7mA 电流 - 输出 / 通道:48mA 电压 - 电源，单路/双路(±):4.5 V ~ 38 V，±2.25 V ~ 19 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) |
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