参数资料
| 型号： | AD5363BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/29页 |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT 8CH SERIAL 56-LFCSP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 1 |
| 设置时间： | 20µs |
| 位数： | 14 |
| 数据接口： | 串行 |
| 转换器数目： | 8 |
| 电压电源： | 双 ± |
| 功率耗散（最大）： | 209mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 56-LFCSP-VQ（8x8） |
| 包装： | 托盘 |
| 输出数目和类型： | 8 电压，单极；8 电压，双极 |
| 采样率（每秒）： | * |
| 配用： | EVAL-AD5363EBZ-ND - BOARD EVALUATION FOR AD5363 |
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AD5362/AD5363
Rev. A | Page 19 of 28
Reference Selection Example
If
Nominal output range = 20 V (10 V to +10 V)
Offset error = ±100 mV
Gain error = ±3%, and
SIGGND = AGND = 0 V
Then
Gain error = ±3%
=> Maximum positive gain error = 3%
=> Output range including gain error = 20 + 0.03(20) = 20.6 V
Offset error = ±100 mV
=> Maximum offset error span = 2(100 mV) = 0.2 V
=> Output range including gain error and offset error =
20.6 V + 0.2 V = 20.8 V
VREF calculation
Actual output range = 20.6 V, that is, 10.3 V to +10.3 V
(centered);
VREF = (10.3 V + 10.3 V)/4 = 5.15 V
If the solution yields an inconvenient reference level, the user
can adopt one of the following approaches:
Use a resistor divider to divide down a convenient, higher
reference level to the required level.
Select a convenient reference level above VREF and modify
the gain and offset registers to digitally downsize the reference.
In this way, the user can use almost any convenient reference
level but can reduce the performance by overcompaction of
the transfer function.
Use a combination of these two approaches.
CALIBRATION
The user can perform a system calibration on the AD5362/
AD5363 to reduce gain and offset errors to below 1 LSB. This
reduction is achieved by calculating new values for the M and
C registers and reprogramming them.
The M and C registers should not be programmed until both
the zero-scale and full-scale errors are calculated.
Reducing Zero-Scale Error
Zero-scale error can be reduced as follows:
1.
Set the output to the lowest possible value.
2.
Measure the actual output voltage and compare it to the
required value. This gives the zero-scale error.
3.
Calculate the number of LSBs equivalent to the error and
add this number to the default value of the C register. Note
that only negative zero-scale error can be reduced.
Reducing Full-Scale Error
Full-scale error can be reduced as follows:
1.
Measure the zero-scale error.
2.
Set the output to the highest possible value.
3.
Measure the actual output voltage and compare it to the
required value. Add this error to the zero-scale error. This
is the span error, which includes the full-scale error.
4.
Calculate the number of LSBs equivalent to the span error
and subtract this number from the default value of the M
register. Note that only positive full-scale error can be
reduced.
AD5362 Calibration Example
This example assumes that a 10 V to +10 V output is required.
The DAC output is set to 10 V but measured at 10.03 V. This
gives a zero-scale error of 30 mV.
1 LSB = 20 V/65,536 = 305.176 μV
30 mV = 98 LSBs
The full-scale error can now be calculated. The output is set to
10 V and a value of 10.02 V is measured. This gives a full-scale
error of +20 mV and a span error of +20 mV – (–30 mV) =
+50 mV.
50 mV = 164 LSBs
The errors can now be removed as follows:
1.
Add 98 LSBs to the default C register value:
(32,768 + 98) = 32,866
2.
Subtract 164 LSBs from the default M register value:
(65,535 164) = 65,371
3.
Program the M register to 65,371; program the C register
to 32,866.
ADDITIONAL CALIBRATION
The techniques described in the previous section are usually
enough to reduce the zero-scale and full-scale errors in most
applications. However, there are limitations whereby the errors
may not be sufficiently reduced. For example, the offset (C)
register can only be used to reduce the offset caused by the
negative zero-scale error. A positive offset cannot be reduced.
Likewise, if the maximum voltage is below the ideal value, that
is, a negative full-scale error, the gain (M) register cannot be
used to increase the gain to compensate for the error.
These limitations can be overcome by increasing the reference
value. With a 2.5 V reference, a 10 V span is achieved. The ideal
voltage range, for the AD5362 or the AD5363, is 5 V to +5 V.
Using a +2.6 V reference increases the range to 5.2 V to +5.2
V.
Clearly, in this case, the offset and gain errors are
insignificant,
and the M and C registers can be used to raise the
negative
voltage to 5 V and then reduce the maximum voltage
to +5 V
to give the most accurate values possible.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD5363BCPZ-REEL7 | 功能描述:IC DAC 14BIT 8CH SERIAL 56-LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Data Converter Fundamentals DAC Architectures 标准包装:750 系列:- 设置时间:7µs 位数:16 数据接口:并联 转换器数目:1 电压电源:双 ± 功率耗散（最大）:100mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-LCC（J 形引线） 供应商设备封装:28-PLCC（11.51x11.51） 包装:带卷 (TR) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:143k |
| AD5363BSTZ | 功能描述:IC DAC 14BIT 8CH SERIAL 52-LQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Data Converter Fundamentals DAC Architectures 标准包装:750 系列:- 设置时间:7µs 位数:16 数据接口:并联 转换器数目:1 电压电源:双 ± 功率耗散（最大）:100mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-LCC（J 形引线） 供应商设备封装:28-PLCC（11.51x11.51） 包装:带卷 (TR) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:143k |
| AD5363BSTZ-REEL | 功能描述:IC DAC 14BIT 8CH SERIAL 52-LQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Data Converter Fundamentals DAC Architectures 标准包装:750 系列:- 设置时间:7µs 位数:16 数据接口:并联 转换器数目:1 电压电源:双 ± 功率耗散（最大）:100mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-LCC（J 形引线） 供应商设备封装:28-PLCC（11.51x11.51） 包装:带卷 (TR) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:143k |
| AD5365D/BIN/883B | 制造商:Analog Devices 功能描述:- Rail/Tube |
| AD536A | 制造商:AD 制造商全称:Analog Devices 功能描述:Integrated Circuit True RMS-to-DC Converter |
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