参数资料
| 型号： | AD5392BSTZ-5 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 20/44页 |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT 8CHAN 3V 52LQFP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 产品变化通告： | AD5390/1/2 Redesign Change 16/May/2012 |
| 设计资源： | 8 to 16 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5390/1/2 (CN0029) AD5390/91/92 Channel Monitor Function (CN0030) |
| 标准包装： | 1 |
| 设置时间： | 8µs |
| 位数： | 14 |
| 数据接口： | I²C，串行 |
| 转换器数目： | 16 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 35mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 52-LQFP |
| 供应商设备封装： | 52-LQFP（10x10） |
| 包装： | 托盘 |
| 输出数目和类型： | 8 电压，单极 |
| 采样率（每秒）： | 125k |
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Data Sheet
AD5390/AD5391/AD5392
Rev. E | Page 27 of 44
I2C SERIAL INTERFACE
The AD5390/AD5391/AD5392 feature an I2C-compatible
2-wire interface consisting of a serial data line (SDA) and a
serial clock line (SCL). SDA and SCL facilitate communication
between the DACs and the master at rates up to 400 kHz.
Figure 6 shows the 2-wire interface timing diagram.
When selecting the I2C operating mode by configuring the
SPI/I2C pin to Logic 0, the device is connected to the I2C bus
as a slave device, that is, no clock is generated by the device.
The AD5390/AD5391/AD5392 have a 7-bit slave address 1010 1
(AD1)(AD0). The five MSBs are hard-coded and the two LSBs
are determined by the state of the AD1 and AD0 pins. The
hardware configuration facility for the AD1 and AD0 pins
allows four of these devices to be configured on the bus.
I2C Data Transfer
One data bit is transferred during each SCL clock cycle. The
data on SDA must remain stable during the high period of the
SCL clock pulse. Changes in SDA while SCL is high are control
signals that configure START and STOP conditions. Both SDA
and SCL are pulled high by the external pull-up resistors when
the I2C bus is not busy.
START and STOP Conditions
A master device initiates communication by issuing a START
condition. A START condition is a high-to-low transition on
SDA with SCL high. A STOP condition is a low-to-high trans-
ition on SDA, while SCL is high. A START condition from the
master signals the beginning of a transmission to the AD539x.
The STOP condition frees the bus. If a repeated START
condition (Sr) is generated instead of a STOP condition, the
bus remains active.
Repeated START Condition
A repeated START (Sr) condition may indicate a change of data
direction on the bus. Sr may be used when the bus master is
writing to several I2C devices and does not want to relinquish
control of the bus.
Acknowledge Bit (ACK)
The acknowledge bit (ACK) is the ninth bit attached to any 8-bit
data-word. An ACK is always generated by the receiving device.
The AD539x devices generate an ACK when receiving an address
or data by pulling SDA low during the ninth clock period.
Monitoring the ACK allows for detection of unsuccessful data
transfers. An unsuccessful data transfer occurs if a receiving
device is busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master should reattempt
communication.
AD539X Slave Addresses
A bus master initiates communication with a slave device by
issuing a START condition followed by the 7-bit slave address.
When idle, the AD539x device waits for a START condition
followed by its slave address. The LSB of the address word is
the read/write (R/W) bit. The AD539x devices are receive
devices only and R/W = 0 when communicating with them.
After receiving the proper address 1010 1(AD1) (AD0), the
AD539x issues an ACK by pulling SDA low for one clock cycle.
The AD539x has four user-programmable addresses determined
by the AD1 and AD0 bits.
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