参数资料
| 型号： | AD5755-1ACPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 29/52页 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT SERIAL 64LFCSP |
| 视频文件： | AD5755: 16-Bit Multi-Channel, Voltage and Current Output DAC |
| 特色产品： | AD5755 / AD5755-1 / AD5757 DACs |
| 标准包装： | 1 |
| 设置时间： | 11µs |
| 位数： | 16 |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 4 |
| 电压电源： | 模拟和数字，双 ± |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 托盘 |
| 输出数目和类型： | 4 电流，4 电压 |
| 采样率（每秒）： | * |
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Data Sheet
AD5755-1
Rev. E | Page 35 of 52
CONTROL REGISTERS
When writing to a control register, the format shown in Table 16
must be used. See Table 9 for information on the configuration
of Bit D23 to Bit D16. The control registers are addressed by
setting the DREG[2:0] bits to 111 and then setting the
CREG[2:0] bits to the appropriate decode address for that
register, according to Table 17. These CREG bits select among
the various control registers.
Main Control Register
The main control register options are shown in Table 18 and
Table 19. See the Device Features section for more information
on the features controlled by the main control register.
Table 16. Writing to a Control Register
MSB
LSB
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12 to D0
R/W
DUT_AD1
DUT_AD0
1
DAC_AD1
DAC_AD0
CREG2
CREG1
CREG0
Data
Table 17. Register Access Decode
CREG2 (D15)
CREG1 (D14)
CREG0 (D13)
Function
0
Slew rate control register (one per channel)
0
1
Main control register
0
1
0
DAC control register (one per channel)
0
1
DC-to-dc control register
1
0
Software register
Table 18. Programming the Main Control Register
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3 to D0
0
1
POC
STATREAD
EWD
WD1
WD0
ShtCctLim
OUTEN_ALL
DCDC_ALL
1 X = don’t care.
Table 19. Main Control Register Functions
Bit
Description
POC
The POC bit determines the state of the voltage output channels during normal operation. Its default value is 0.
POC = 0. The output goes to the value set by the POC hardware pin when the voltage output is not enabled (default).
POC = 1. The output goes to the opposite value of the POC hardware pin if the voltage output is not enabled.
STATREAD
Enable status readback during a write. See the Device Features section.
STATREAD = 1, enable.
STATREAD = 0, disable (default).
EWD
Enable watchdog timer. See the Device Features section for more information.
EWD = 1, enable watchdog.
EWD = 0, disable watchdog (default).
WD1, WD0
Timeout select bits. Used to select the timeout period for the watchdog timer.
WD1
WD0
Timeout Period (ms)
0
5
0
1
10
1
0
100
1
200
ShtCctLim
Programmable short-circuit limit on the V
OUT_x pin in the event of a short-circuit condition.
0 = 16 mA (default).
1 = 8 mA.
OUTEN_ALL
Enables the output on all four DACs simultaneously.
Do not use the OUTEN_ALL bit when using the OUTEN bit in the DAC control register.
DCDC_ALL
When set, powers up the dc-to-dc converter on all four channels simultaneously.
To power down the dc-to-dc converters, all channel outputs must first be disabled.
Do not use the DCDC_ALL bit when using the DC_DC bit in the DAC control register.
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