参数资料
| 型号： | AD5755-1ACPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 37/52页 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT SERIAL 64LFCSP |
| 视频文件： | AD5755: 16-Bit Multi-Channel, Voltage and Current Output DAC |
| 特色产品： | AD5755 / AD5755-1 / AD5757 DACs |
| 标准包装： | 1 |
| 设置时间： | 11µs |
| 位数： | 16 |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 4 |
| 电压电源： | 模拟和数字，双 ± |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 托盘 |
| 输出数目和类型： | 4 电流，4 电压 |
| 采样率（每秒）： | * |
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AD5755-1
Data Sheet
Rev. E | Page 42 of 52
directly to the gain/TUE error of the AD5755-1 with the exter-
HART
The AD5755-1 has four CHART pins, one corresponding to
each output channels. A HART signal can be coupled into these
pins. The HART signal appears on the corresponding current
output, if the output is enabled. Table 31 shows the recommended
input voltages for the HART signal at the CHART pin. If these
voltages are used, the current output should meet the HART
amplitude specifications. Figure 79 shows the recommended
circuit for attenuating and coupling in the HART signal.
Table 31. CHART Input Voltage to HART Output Current
R
SET
CHART Input
Voltage
Current Output
(HART)
Internal R
SET
150 mV p-p
1 mA p-p
External R
SET
170 mV p-p
1 mA p-p
09226-
076
HART MODEM
OUTPUT
C1
C2
CHARTx
Figure 79. Coupling HART Signal
A minimum capacitance of C1 + C2 is required to ensure that
the 1.2 kHz and 2.2 kHz HART frequencies are not significantly
attenuated at the output. The recommended values are C1 =
22 nF, C2 = 47 nF.
Digitally controlling the slew rate of the output is necessary to
meet the analog rate of change requirements for HART.
DIGITAL SLEW RATE CONTROL
The slew rate control feature of the AD5755-1 allows the user to
control the rate at which the output value changes. This feature
is available on both the current and voltage outputs. With the
slew rate control feature disabled, the output value changes at a
rate limited by the output drive circuitry and the attached load.
To reduce the slew rate, this can be achieved by enabling the
slew rate control feature. With the feature enabled via the SREN
bit of the slew rate control register (see Table 26), the output,
instead of slewing directly between two values, steps digitally at
a rate defined by two parameters accessible via the slew rate
control register, as shown in Table 26.
The parameters are SR_CLOCK and SR_STEP. SR_CLOCK
defines the rate at which the digital slew is updated, for
example, if the selected update rate is 8 kHz, the output updates
every 125 s. In conjunction with this, SR_STEP defines by how
much the output value changes at each update. Together, both
parameters define the rate of change of the output value. Table 32
and Table 33 outline the range of values for both the
SR_CLOCK and SR_STEP parameters.
Table 32. Slew Rate Update Clock Options
SR_CLOCK
Update Clock Frequency (Hz)1
0000
64 k
0001
32 k
0010
16 k
0011
8 k
0100
4 k
0101
2 k
0110
1 k
0111
500
1000
250
1001
125
1010
64
1011
32
1100
16
1101
8
1110
4
1111
0.5
1 These clock frequencies are divided down from the 13 MHz internal
Table 33. Slew Rate Step Size Options
SR_STEP
Step Size (LSBs)
000
1
001
2
010
4
011
16
100
32
101
64
110
128
111
256
The following equation describes the slew rate as a function of
the step size, the update clock frequency, and the LSB size:
Size
LSB
Frequency
Clock
Update
Size
Step
Change
Output
Time
Slew
×
=
where:
Slew Time is expressed in seconds.
Output Change is expressed in amps for IOUT_x or volts for VOUT_x.
When the slew rate control feature is enabled, all output changes
occur at the programmed slew rate (see the DC-to-DC Converter
Settling Time section for additional information). For example,
if the CLEAR pin is asserted, the output slews to the clear value
at the programmed slew rate (assuming that the clear channel is
enabled to be cleared). If a number of channels are enabled for
slew, care must be taken when asserting the CLEAR pin. If one
of the channels is slewing when CLEAR is asserted, other chan-
nels may change directly to their clear values not under slew
rate control. The update clock frequency for any given value is
the same for all output ranges. The step size, however, varies
across output ranges for a given value of step size because the
LSB size is different for each output range.
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| AD5755-1ACPZ-REEL7 | 功能描述:IC DAC 16BIT SERIAL 64LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Data Converter Fundamentals DAC Architectures 标准包装:750 系列:- 设置时间:7µs 位数:16 数据接口:并联 转换器数目:1 电压电源:双 ± 功率耗散（最大）:100mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-LCC（J 形引线） 供应商设备封装:28-PLCC（11.51x11.51） 包装:带卷 (TR) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:143k |
| AD5755-1X | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad Channel, 16-Bit, Serial Input, 4-20mA & Voltage Output DAC, Dynamic Power Control, HART Connectivity |
| AD5755ACPZ | 功能描述:数模转换器- DAC 16Bit Quad V/I DAC with Dynamic Power RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
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