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参数资料
| 型号： | AD5764CSUZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/28页 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT QUAD BIPO 32-TQFP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 产品变化通告： | AD5764(R), AD5744R Product Change 04/Sept/2009 |
| 设计资源： | High Accuracy, Bipolar Voltage Output Digital-to-Analog Conversion Using AD5764 (CN0006) |
| 标准包装： | 500 |
| 设置时间： | 8µs |
| 位数： | 16 |
| 数据接口： | 串行 |
| 转换器数目： | 4 |
| 电压电源： | 双 ± |
| 功率耗散（最大）： | 275 mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-TQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 4 电压，双极 |
| 采样率（每秒）： | 1.26M |
| 配用： | EVAL-AD5764EBZ-ND - BOARD EVAL FOR AD5764 |
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Data Sheet
AD5764
Rev. F | Page 23 of 28
OFFSET AND GAIN ADJUSTMENT WORKED
EXAMPLE
Using the information provided in the Fine Gain Register and
Offset Register sections, the following worked example demon-
strates how the AD5764 functions can be used to eliminate both
offset and gain errors. Because the AD5764 is factory calibrated,
offset and gain errors should be negligible. However, errors can
be introduced by the system that the AD5764 is operating within;
for example, a voltage reference value that is not equal to 5 V
introduces a gain error. An output range of ±10 V and twos
complement data coding is assumed.
Removing Offset Error
The AD5764 can eliminate an offset error in the range of 4.88 mV
to +4.84 mV with a step size of of a 16-bit LSB.
Calculate the step size of the offset adjustment.
μV
14
.
38
8
2
20
16
=
×
=
Size
Step
Adjust
Offset
Measure the offset error by programming 0x0000 to the data
register and measuring the resulting output voltage. For this
example, the measured value is 614 μV.
Calculate the number of offset adjustment steps that this value
represents.
Steps
16
μV
14
.
38
μV
614
=
Size
Step
Offset
Value
Offset
Measured
Steps
of
Number
The offset error measured is positive, therefore, a negative
adjustment of 16 steps is required. The offset register is eight
bits wide and the coding is twos complement. The required
offset register value can be calculated as follows:
Convert the adjustment value to binary: 00010000.
Convert this to a negative twos complement number by inverting
all bits and adding 1 to obtain 11110000, the value that should
be programmed to the offset register.
Note that this twos complement conversion is not necessary in the
case of a positive offset adjustment. The value to be programmed to
the offset register is simply the binary representation of the
adjustment value.
Removing Gain Error
The AD5764 can eliminate a gain error at negative full-scale
output in the range of 9.77 mV to +9.46 mV with a step size of
of a 16-bit LSB.
Calculate the step size of the gain adjustment.
μV
59
.
152
2
20
16
=
×
=
Size
Step
Adjust
Gain
Measure the gain error by programming 0x8000 to the data
register and measuring the resulting output voltage. The gain
error is the difference between this value and 10 V. For this
example, the gain error is 1.2 mV.
Calculate how many gain adjustment steps this value represents.
Steps
8
μV
59
.
152
mV
2
.
1
=
Size
Step
Gain
Value
Gain
Measured
Steps
of
Number
The gain error measured is negative (in terms of magnitude);
therefore, a positive adjustment of eight steps is required. The
gain register is 6 bits wide and the coding is twos complement,
the required gain register value can be determined as follows:
Convert the adjustment value to binary: 001000.
The value to be programmed to the gain register is simply this
binary number.
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| AD5764RBSUZ | 功能描述:IC DAC 16BIT QUAD VOUT 32-TQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1,000 系列:- 设置时间:1µs 位数:8 数据接口:串行 转换器数目:8 电压电源:双 ± 功率耗散（最大）:941mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC W 包装:带卷 (TR) 输出数目和类型:8 电压，单极 采样率（每秒）:* |
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