参数资料
型号: AD676KNZ
厂商: Analog Devices Inc
文件页数: 11/16页
文件大小: 0K
描述: IC ADC 16BIT 100KSPS 28-DIP
标准包装: 1
位数: 16
采样率(每秒): 100k
数据接口: 并联
转换器数目: 2
功率耗散(最大): 480mW
电压电源: 模拟和数字,双 ±
工作温度: 0°C ~ 70°C
安装类型: 通孔
封装/外壳: 28-DIP(0.600",15.24mm)
供应商设备封装: 28-PDIP
包装: 管件
输入数目和类型: 1 个单端,双极
AD676
REV. A
–4–
TIMING SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Units
Conversion Time
2
tC
10
1000
s
CLK Period
3
tCLK
480
ns
Calibration Time
tCT
85,530
tCLK
Sampling Time (Included in tC)tS
2
s
CAL to BUSY Delay
tCALB
75
150
ns
BUSY to SAMPLE Delay
tBS
2
s
SAMPLE to BUSY Delay
tSB
15
100
ns
CLK HIGH
4
tCH
50
ns
CLK LOW
4
tCL
50
ns
SAMPLE LOW to 1st CLK Delay
tSC
50
ns
SAMPLE LOW
tSL
100
ns
Output Delay
tOD
125
200
ns
Status Delay
tSD
50
ns
CAL HIGH Time
tCALH
50
ns
NOTES
1See the “CONVERSION CONTROL” and “AUTOCALIBRATION” sections for detailed explanations of the above timing.
2Depends upon external clock frequency; includes acquisition time and conversion time. The maximum conversion time is specified to account for the droop of the
internal sample/hold function. Longer conversion times may degrade performance. See “General Conversion Guidelines” for additional explanation of maximum con-
version time.
3580 ns is recommended for optimal accuracy over temperature.
4t
CH + tCL = tCLK and must be greater than 480 ns.
CAL
BUSY
CLK
t
CH
t
CL
t
CLK
tCALB
t
OD
t
CT
CALH
t
Figure 1. Calibration Timing
SAMPLE
(INPUT)
CLK
(INPUT)
BIT 1 – BIT 16
(OUTPUTS)
BUSY
(OUTPUT)
1
234
5
t
S
t
SL
t
SC
t
CLK
t
CL
t
CH
t
OD
t
SD
t
SB
t
BS
t
C
13
14
15
16
17
(PREVIOUS CONVERSION)
(NEW DATA)
Figure 2a. General Conversion Timing
SAMPLE
(INPUT)
CLK
(INPUT)
BIT 1 – BIT 16
(OUTPUTS)
BUSY
(OUTPUT)
1
234
5
t
S
t
SL
t
SC
t
CLK
t
CL
t
CH
t
OD
t
SD
t
SB
t
BS
t
C
13
14
15
16
17
t
S
(PREVIOUS CONVERSION)
(NEW DATA)
Figure 2b. Continuous Conversion Timing
(TMIN to TMAX VCC = +12 V
5%, VEE = –12 V
5%, VDD = +5 V
10%, VREF = 10.0 V)
1
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