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| 型号： | AD73311 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Low Cost, Low Power CMOS General Purpose Analog Front End Processor(低成本、低功耗、CMOS通用模拟前端处理器) |
| 中文描述： | 低成本，低功耗CMOS通用模拟前端处理器（低成本，低功耗，的CMOS通用模拟前端处理器） |
| 文件页数： | 26/36页 |
| 文件大小： | 290K |
| 代理商： | AD73311 |
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AD73311
–26–
REV. A
Cascade Operation
Where it is required to configure a cascade of up to eight de-
vices, it is necessary to ensure that the timing of the SE and
RESET
signals is synchronized at each device in the cascade. A
simple D type flip flop is sufficient to sync each signal to the
master clock MCLK, as in Figure 30.
1/2
74HC74
D
CLK
Q
DSP CONTROL
TO SE
MCLK
SE SIGNAL SYNCHRONIZED
TO MCLK
DSP CONTROL
TO
RESET
MCLK
RESET
SIGNAL SYNCHRONIZED
TO MCLK
1/2
74HC74
D
CLK
Q
Figure 30. SE and
RESET
Sync Circuit for Cascaded
Operation
Connection of a cascade of devices to a DSP, as shown in Fig-
ure 31, is no more complicated than connecting a single device.
Instead of connecting the SDO and SDOFS to the DSP’s Rx
port, these are now daisy-chained to the SDI and SDIFS of the
next device in the cascade. The SDO and SDOFS of the final
device in the cascade are connected to the DSP’s Rx port to
complete the cascade. SE and
RESETB
on all devices are fed
from the signals that were synchronized with the MCLK using
the circuit as described above. The SCLK from only one device
need be connected to the DSP’s SCLK input(s) as all devices
will be running at the same SCLK frequency and phase.
SDIFS
SDI
SCLK
SDO
SDOFS
TFS
DT
SCLK
DR
RFS
MCLK
SE
RESET
DEVICE 1
FL0
FL1
SDIFS
SDI
SCLK
SDO
SDOFS
MCLK
SE
RESET
DEVICE 2
74HC74
D1
D2
Q1
Q2
CLK
AD73311
CODEC
AD73311
CODEC
ADSP-2181
DSP
Figure 31. Connection of Two AD73311s Cascaded to
ADSP-2181
Grounding and Layout
Since the analog inputs to the AD73311 are differential, most of
the voltages in the analog modulator are common-mode volt-
ages. The excellent common-mode rejection of the part will
remove common-mode noise on these inputs. The analog and
digital supplies of the AD73311 are independent and separately
pinned out to minimize coupling between analog and digital
sections of the device. The digital filters on the encoder section
will provide rejection of broadband noise on the power supplies,
except at integer multiples of the modulator sampling frequency.
The digital filters also remove noise from the analog inputs
provided the noise source does not saturate the analog modula-
tor. However, because the resolution of the AD73311’s ADC is
high, and the noise levels from the AD73311 are so low, care
must be taken with regard to grounding and layout.
The printed circuit board that houses the AD73311 should be
designed so the analog and digital sections are separated and
confined to certain sections of the board. The AD73311 pin
configuration offers a major advantage in that its analog and
digital interfaces are connected on opposite sides of the package.
This facilitates the use of ground planes that can be easily sepa-
rated, as shown in Figure 32. A minimum etch technique is
generally best for ground planes as it gives the best shielding.
Digital and analog ground planes should be joined in only one
place. If this connection is close to the device, it is recom-
mended to use a ferrite bead inductor as shown in Figure 32.
DIGITAL GROUND
ANALOG GROUND
Figure 32. Ground Plane Layout
Avoid running digital lines under the device for they will couple
noise onto the die. The analog ground plane should be allowed
to run under the AD73311 to avoid noise coupling. The power
supply lines to the AD73311 should use as large a trace as pos-
sible to provide low impedance paths and reduce the effects of
glitches on the power supply lines. Fast switching signals such as
clocks should be shielded with digital ground to avoid radiating
noise to other sections of the board, and clock signals should
never be run near the analog inputs. Traces on opposite sides of
the board should run at right angles to each other. This will
reduce the effects of feedthrough through the board. A microstrip
technique is by far the best but is not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to ground planes while signals are placed
on the other side.
相关PDF资料 |
PDF描述 |
|---|---|
| AD73322LARU | Low Cost, Low Power CMOS General-Purpose Dual Analog Front End |
| AD73322AR | Low Cost, Low Power CMOS General-Purpose Dual Analog Front End |
| AD73322AST | Low Cost, Low Power CMOS General-Purpose Dual Analog Front End |
| AD73322LAR | Low Cost, Low Power CMOS General-Purpose Dual Analog Front End |
| AD73322LAST | Low Cost, Low Power CMOS General-Purpose Dual Analog Front End |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD73311AR | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:SPEECH & TELEPHONY CODEC I.C. - Bulk 制造商:Analog Devices 功能描述:SPEECH/TELEPHONY CODEC SMD 73311 |
| AD73311AR-REEL | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin SOIC W T/R |
| AD73311ARS | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin SSOP |
| AD73311ARS-REEL | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin SSOP T/R 制造商:Rochester Electronics LLC 功能描述:SPEECH & TELEPHONY CODEC I.C. - Tape and Reel |
| AD73311ARSZ | 功能描述:IC ANALOG FRONT END 20-SSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
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