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| 型号： | AD73311 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Low Cost, Low Power CMOS General Purpose Analog Front End Processor(低成本、低功耗、CMOS通用模拟前端处理器) |
| 中文描述： | 低成本，低功耗CMOS通用模拟前端处理器（低成本，低功耗，的CMOS通用模拟前端处理器） |
| 文件页数： | 6/36页 |
| 文件大小： | 290K |
| 代理商： | AD73311 |
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AD73311
–6–
REV. A
Table III. Signal Ranges
3 V Power Supply
5VEN = 0
1.2 V
±
10%
1.2 V
±
10%
5 V Power Supply
5VEN = 0
5VEN = 1
V
REFCAP
V
REFOUT
ADC
1.2 V
2.4 V
1.2 V
2.4 V
Maximum Input Range
at V
IN
Nominal Reference Level
1.578 V p-p
1.0954 V p-p
1.578 V p-p
1.0954 V p-p
3.156 V p-p
2.1908 V p-p
DAC
Maximum Voltage
Output Swing
Single-Ended
Differential
Nominal Voltage
Output Swing
Single-Ended
Differential
Output Bias Voltage
1.578 V p-p
3.156 V p-p
1.578 V p-p
3.156 V p-p
3.156 V p-p
6.312 V p-p
1.0954 V p-p
2.1909 V p-p
V
REFOUT
1.0954 V p-p
2.1909 V p-p
V
REFOUT
2.1908 V p-p
4.3818 V p-p
V
REFOUT
TIMING CHARACTERISTICS
Limit at
T
A
= –40
8
C to +85
8
C
Parameter
Units
Description
Clock Signals
t
1
t
2
t
3
Serial Port
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
See Figure 1
MCLK Period
MCLK Width High
MCLK Width Low
See Figures 3 and 4
SCLK Period
SCLK Width High
SCLK Width Low
SDI/SDIFS Setup Before SCLK Low
SDI/SDIFS Hold After SCLK Low
SDOFS Delay from SCLK High
SDOFS Hold After SCLK High
SDO Hold After SCLK High
SDO Delay from SCLK High
SCLK Delay from MCLK
61
24.4
24.4
ns min
ns min
ns min
t
1
0.4
×
t
1
0.4
×
t
1
20
0
10
10
10
10
30
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns max
(AVDD = +3 V
6
10%; DVDD = +3 V
6
10%; AGND = DGND = 0 V; T
A
= T
MlN
to T
MAX
, unless
otherwise noted)
Table II. Current Summary (AVDD = DVDD = +5.5 V)
Internal Digital
External Interface
Current Current
Current
8.5
6
2
14.5
6
2
0.8
0
0
Analog
MCLK
ON
YES
YES
NO
Conditions
ADC On Only
ADC and DAC On
REFCAP On Only
REFCAP and
REFOUT On Only
All Sections Off
Total Current
16.5
22.5
0.8
SE
1
1
0
Comments
REFOUT Disabled
REFOUT Disabled
REFOUT Disabled
3.5
0
0
1.5
0
0
3.5
1.5
0
0
NO
YES
MCLK Active Levels Equal to
0 V and DVDD
Digital Inputs Static and
Equal to 0 V or DVDD
All Sections Off
0
0.01
0
0.01
0
NO
The above values are in mA and are typical values unless otherwise noted.
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PDF描述 |
|---|---|
| AD73322LARU | Low Cost, Low Power CMOS General-Purpose Dual Analog Front End |
| AD73322AR | Low Cost, Low Power CMOS General-Purpose Dual Analog Front End |
| AD73322AST | Low Cost, Low Power CMOS General-Purpose Dual Analog Front End |
| AD73322LAR | Low Cost, Low Power CMOS General-Purpose Dual Analog Front End |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD73311AR | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:SPEECH & TELEPHONY CODEC I.C. - Bulk 制造商:Analog Devices 功能描述:SPEECH/TELEPHONY CODEC SMD 73311 |
| AD73311AR-REEL | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin SOIC W T/R |
| AD73311ARS | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin SSOP |
| AD73311ARS-REEL | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin SSOP T/R 制造商:Rochester Electronics LLC 功能描述:SPEECH & TELEPHONY CODEC I.C. - Tape and Reel |
| AD73311ARSZ | 功能描述:IC ANALOG FRONT END 20-SSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
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