AD73311L
–11–
REV. PrA1
09/98
DATA
TECHNCAL
Decoder C hannel
sigma-delta modulator, a single bit digital-to-analog converter
(DAC), an analog smoothing filter and a programmable gain
amplifier with differential output.
a. Analog Antialias Filter Transfer Function
final output of the ADC block. In 16-bit Data Mode this value
is left shifted with the LSB being set to 0. For input values
equal to or greater than positive full scale, however, the output
word is set at 0x7FFF, which has the LSB set to 1. In mixed
Control/Data Mode, the resolution is fixed at 15 bits, with the
MSB of the
16-bit transfer being used as a flag bit to indicate either control
or data in the frame.
F
B
= 4kHz
FS
INIT
= DMCLK/8
F
B
= 4kHz
b. Analog Sigma-Delta Modulator Transfer Function
FS
INIT
= DMCLK/8
SIGNAL TRANSFER FUNCTION
NOISE TRANSFER FUNCTION
F
B
= 4kHz
FS
INTER
= DMCLK/256
c. Digital Decimator Transfer Function
F
B
= 4kHz
FS
FINAL
= 8kHz
FS
INTER
= DMCLK/256
d. Final Filter LPF (HPF) Transfer Function
Figure 7. AD73311L ADC Frequency Responses
Decimation F ilter
T he digital filter used in the AD73311L carries out two impor-
tant functions. Firstly, it removes the out-of-band quantization
noise, which is shaped by the analog modulator and secondly,
it decimates the high frequency bit-stream to a lower rate 15-
bit word.
T he antialiasing decimation filter is a sinc-cubed digital filter
that reduces the sampling rate from DMCLK /8 to DMCLK /
256, and increases the resolution from a single bit to 15 bits. Its
Z transform is given as: [(1–Z
–32
)/(1–Z
–1
)]
3
. T his ensures a
minimal group delay of 25 μs.
AD C C oding
T he ADC coding scheme is in twos complement format (see
Figure 8). T he output words are formed by the decimation
filter, which grows the word length from the single-bit output
of the sigma-delta modulator to a 15-bit word, which is the
requirements and available MIPS. T he filtering in Figures 7a
through 7c is implemented in the AD73311L.
V
INN
V
INP
V
REF
+ (V
REF
x 0.32875)
V
REF
V
REF
- (V
REF
x 0.32875)
10...00
00...00
01...11
ADC CODE DIFFERENTIAL
V
INN
V
INP
V
REF
+ (V
REF
x 0.6575)
V
REF
V
REF
- (V
REF
x 0.6575)
10...00
00...00
01...11
ADC CODE SINGLE ENDED
ANALOG
INPUT
ANALOG
INPUT
Figure 8. ADC Transfer Function
D AC C oding
T he DAC coding scheme is in twos complement format with
0x7FFF being full-scale positive and 0x8000 being full-scale
negative.
Interpolation F ilter
T he anti-imaging interpolation filter is a sinc-cubed digital
filter which up-samples the 16-bit input words from a rate of
DMCLK /256 to a rate of DMCLK /8 while filtering to
attenuate images produced by the interpolation process. Its Z
transform is given as: [(1–Z
–32
)/(1–Z
–1
)]
3
. T he DAC receives
16-bit samples from the host DSP processor at a rate of
DMCLK /256. If the host processor fails to write a new value to
the serial port, the existing (previous) data is read again. T he
data stream is filtered by the anti-imaging interpolation filter,
but there is an option to bypass the interpolator for the
minimum group delay configuration by setting the IBYP bit
(CRE:5) of Control register E. T he interpolation filter has the
same characteristics as the ADC’s antialiasing decimation filter.
T he output of the interpolation filter is fed to the DAC’s digital
sigma-delta modulator, which converts the 16-bit data to 1-bit
samples at a rate of DMCLK /8. T he modulator noise-shapes
the signal so that errors inherent to the process are minimized
in the passband of the converter. T he bit-stream output of the