AD73311L
–14–
REV. PrA1
09/98
DATA
TECHNCAL
all sections to be powered up by setting the bit. Using this
T able X . Control Word Description
circumstances this can reduce the group delay when the ADC
and DAC are used to process data in series. Appendix E details
how the DAC advance feature can be used.
NOT E: T he DAC advance register should be changed before
the DAC section is powered up.
T able VIII. DAC T iming Control
DA4
DA3
DA2
DA1
DA0
T ime Advance*
0
0
0
—
1
1
0
0
0
—
1
1
0
0
0
—
1
1
0
0
1
—
1
1
0
1
0
—
0
1
0 ns
488.2 ns
976.5 ns
—
14.64 μs
15.13 μs
*DMCLK = 16.384 MHz.
OPE RAT ION
Resetting the AD73311L
T he pin
RESET
resets all the control registers. All registers
are reset to zero indicating that the default SCL K rate
(DMCLK /8) and sample rate (DMCLK /2048) are at a mini-
mum to ensure that slow speed DSP engines can communicate
effectively. As well as resetting the control registers using the
RESET
pin, the device can be reset using the
RESET
bit (CRA:7)
in Control Register A. Both hardware and software resets
require 4 DMCLK cycles. On reset, DAT A/
PGM
(CRA:0) is
set to 0 (default condition) thus enabling Program Mode. T he
reset conditions ensure that the device must be programmed to
the correct settings after power-up or reset. Following a reset,
the SDOFS will be asserted 280 DMCLK cycles after
RESET
going high. T he data that is output following
RESET
and
during Program Mode is random and contains no valid infor-
mation until either data or mixed mode is set.
Power Management
enabled separately by programming the power control register
CRC. It allows certain sections to be powered down if not
required, which adds to the device’s flexibility in that the user
need not incur the penalty of having to provide power for a
certain section if it is not necessary to their design. T he power
control register provides individual control settings for the
Control
Frame
Description
Bit 15
Control/
Data
When set high, it signifies a control word in Program or Mixed Program/Data Modes. When
set low, it signifies a data word in Mixed Program/Data Mode or an invalid control word in
Program Mode.
When set low, it tells the device that the data field is to be written to the register selected by
the register field setting provided the address field is zero. When set high, it tells the device
that the selected register is to be written to the data field in the input serial register and that
the new control word is to be output from the device via the serial output.
T his 3-bit field holds the address information. Only when this field is zero is a device se-
lected. If the address is not zero, it is decremented and the control word is passed out of
the device via the serial output.
T his 3-bit field is used to select one of the five control registers on the AD73311L.
T his 8-bit field holds the data that is to be written to or read from the selected register
provided the address field is zero.
Bit 14
Read/
Write
Bit 13–11
Device Address
Bits 10–8
Bits 7–0
Register Address
Register Data
T able IX . Control Register Map
Address (Binary)
Name
Description
T ype
Width
Reset Setting (Hex)
000
001
010
011
100
101 to 111
CRA
CRB
CRC
CRD
CRE
Control Register A
Control Register B
Control Register C
Control Register D
Control Register E
Reserved
R/W
R/W
R/W
R/W
R/W
8
8
8
8
8
0x00
0x00
0x00
0x00
0x00