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参数资料
| 型号： | AD73311L |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Low Cost, Low Power CMOS General Purpose Analog Front End Processor(低成本，低功耗的CMOS通用双模拟前端处理器) |
| 中文描述： | 低成本，低功耗CMOS通用模拟前端处理器（低成本，低功耗的的CMOS通用双模拟前端处理器） |
| 文件页数： | 12/20页 |
| 文件大小： | 132K |
| 代理商： | AD73311L |
AD73311L
–12–
REV. PrA1
09/98
DATA
TECHNCAL
certain configurations, data can be written to the device to
coincide with the output sample being shifted out of the serial
register—see section on interfacing devices. T he serial clock
rate (CRB:2–3) defines how many 16-bit words can be written
to a device before the next output sample event will happen.
T he SPORT block diagram, shown in Figure 9, details the five
control registers (A–E), external MCLK to internal DMCLK
divider and serial clock divider. T he divider rates are controlled
by the setting of Control Register B. T he AD73311L features a
master clock divider that allows users the flexibility of dividing
externally available high frequency DSP or CPU clocks to
generate a lower frequency master clock internally in the codec
which may be more suitable for either serial transfer or
sampling rate requirements. T he master clock divider has five
divider options (÷1 default condition, ÷2, ÷3, ÷4, ÷5) that are
set by loading the master clock divider field in Register B with
the appropriate code. Once the internal device master clock
(DMCLK) has been set using the master clock divider, the
sample rate and serial clock settings are derived from DMCLK .
T he SPORT can work at four different serial clock (SCLK )
rates: chosen from DMC L K , DMC L K /2, DMC L K /4 or
DMC L K /8, where DMC L K is the internal or device master
clock resulting from the external or pin master clock being
divided by the master clock divider. When working at the lower
SCLK rate of DMCLK /8, which is intended for interfacing
with slower DSPs, the SPORT will support a maximum of two
devices in cascade with the sample rate of DMCLK /256.
sigma-delta modulator is fed to the single bit DAC where it is
converted to an analog voltage.
Analog Smoothing F ilter & PGA
T he output of the single-bit DAC is sampled at DMCLK /8,
therefore it is necessary to filter the output to reconstruct the
low frequency signal. T he decoder’s analog smoothing filter
consists of a continuous-time filter preceded by a third-order
switched-capacitor filter. T he continuous-time filter forms part
of the output programmable gain amplifier (PGA). T he PGA
can be used to adjust the output signal level from –15 dB to
+6 dB in 3 dB steps, as shown in T able V. T he PGA gain is
set by bits OGS0, OGS1 and OGS2 (C RD:4-6) in C ontrol
Register D.
T able V. PGA Settings for the Decoder Channel
OG2
OG1
OG0
Gain (dB)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+6
+3
0
–3
–6
–9
–12
–15
Differential Output Amplifiers
T he decoder has a differential analog output pair (VOUT P and
VOUT N). T he output channel can be muted by setting the
MUT E bit (CRD:7) in Control Register D. T he output signal
is dc-biased to the codec’s on-chip voltage reference.
Voltage Reference
T he AD73311L reference, REFCAP, is a bandgap reference
that provides a low noise, temperature-compensated reference
to the DAC and ADC. A buffered version of the reference is
also made available on the REFOUT pin and can be used to
bias other external analog circuitry. T he reference has a default
nominal value of 1.2 V but can be set to a nominal value of
2.4 V by setting the 5VEN bit (CRC:7) of CRC. T he 5 V mode
is generally only usable when V
DD
= 5 V.
T he reference output (REFOUT ) can be enabled for biasing
external circuitry by setting the RU bit (CRC:6) of CRC.
Serial Port (SPORT )
T he codec communicates with a host processor via the bidirec-
tional synchronous serial port (SPORT ) which is compatible
with most modern DSPs. T he SPORT is used to transmit and
receive digital data and control information.
In both transmit and receive modes, data is transferred at the
serial clock (SCLK ) rate with the MSB being transferred first.
Due to the fact that the SPORT uses a common serial register for
serial input and output, communications between an AD73311L
codec and a host processor (DSP engine) must always be
initiated by the codec itself. T his ensures that there is no
danger of the information being sent to the codec being cor-
rupted by ADC samples being output by the codec.
SPORT Overview
T he AD73311L SPORT is a flexible, full-duplex, synchronous
serial port whose protocol has been designed to allow up to
eight AD73311L devices to be connected, in cascade, to a
single DSP via a six-wire interface. It has a very flexible
architecture that can be configured by programming two of the
internal control registers. T he AD73311L SPORT has three
distinct modes of operation: Control Mode, Data Mode and
Mixed Control/Data Mode.
In Control Mode (CRA:0 = 0), the device’s internal configura-
tion can be programmed by writing to the five internal control
registers. In this mode, control information can be written to or
read from the codec. In Data Mode (CRA:0 = 1), information
that is sent to the device is used to update the decoder section
(DAC), while the encoder section (ADC) data is read from the
device. In this mode, only DAC and ADC data is written to or
read from the device. Mixed mode (CRA:0 = 1 and CRA:1 =
1) allows the user to choose whether the information being sent
to the device contains either control information or DAC data.
T his is achieved by using the MSB of the 16-bit frame as a flag
bit. Mixed mode reduces the resolution to 15 bits with the
MSB being used to indicate whether the information in the 16-
bit frame is control information or DAC/ADC data.
T he SPORT features a single 16-bit serial register that is used
for both input and output data transfers. As the input and
tions that must be observed. T he primary precaution is that no
information must be written to the SPORT without reference
to an output sample event, which is when the serial register will
be overwritten with the latest ADC sample word. Once the
SPORT starts to output the latest ADC word then it is safe for
the DSP to write new control or data words to the codec. In
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD73311LAR | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:SINGLE-CHANNEL AFE I.C. - Bulk |
| AD73311LAR-REEL | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:SINGLE-CHANNEL AFE I.C. - Tape and Reel |
| AD73311LAR-REEL7 | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:SINGLE-CHANNEL AFE I.C. - Tape and Reel |
| AD73311LARS | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin SSOP 制造商:Rochester Electronics LLC 功能描述:SINGLE-CHANNEL AFE I.C. - Bulk 制造商:Analog Devices 功能描述:IC AUDIO CODEC |
| AD73311LARS-REEL | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin SSOP T/R |
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