REV. A
AD73311L
–13–
Table X. Control Word Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
C/
D
R/
W
Device Address
Register Address
Register Data
Control
Frame
Description
Bit 15
Control/
Data
When set high, it signi
fi
es a control word in Program or Mixed Program/Data Modes. When
set low, it signi
fi
es a data word in Mixed Program/Data Mode or an invalid control word in
Program Mode.
When set low, it tells the device that the data
fi
eld is to be written to the register selected by
the register
fi
eld setting provided the address
fi
eld is zero. When set high, it tells the device
that the selected register is to be written to the data
fi
eld in the input serial register and that
the new control word is to be output from the device via the serial output.
This 3-bit
fi
eld holds the address information. Only when this
fi
eld is zero is a device selected.
If the address is not zero, it is decremented and the control word is passed out of the device
via the serial output.
This 3-bit
fi
eld is used to select one of the
fi
ve control registers on the AD73311L.
This 8-bit
fi
eld holds the data that is to be written to or read from the selected register provided
the address
fi
eld is zero.
Bit 14
Read/
Write
Bits 13
–
11
Device Address
Bits 10
–
8
Bits 7
–
0
Register Address
Register Data
Table IX. Control Register Map
Address (Binary)
Name
Description
Type
Width
Reset Setting (Hex)
000
001
010
011
100
101
110 to 111
CRA
CRB
CRC
CRD
CRE
CRF
Control Register A
Control Register B
Control Register C
Control Register D
Control Register E
Control Register F
Reserved
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
8
8
8
8
8
8
0x00
0x00
0x00
0x00
0x00
0x00
Table VIII. DAC Timing Control
DA4
DA3
DA2
DA1
DA0
Time Advance
*
0
0
0
—
1
1
0
0
0
—
1
1
0
0
0
—
1
1
0
0
1
—
1
1
0
1
0
—
0
1
0 ns
488.2 ns
976.5 ns
—
14.64
μ
s
15.13
μ
s
*
DMCLK = 16.384 MHz.
OPERATION
Resetting the AD73311L
The pin
RESET
resets all the control registers. All registers are
reset to zero indicating that the default SCLK rate (DMCLK/8)
and sample rate (DMCLK/2048) are at a minimum to ensure
that slow speed DSP engines can communicate effectively. As
well as resetting the control registers using the
RESET
pin, the
device can be reset using the
RESET
bit (CRA:7) in Control
Register A. Both hardware and software resets require 4 DMCLK
cycles. On reset, DATA/
PGM
(CRA:0) is set to 0 (default condi-
tion) thus enabling Program Mode. The reset conditions ensure
that the device must be programmed to the correct settings after
power-up or reset. Following a reset, the SDOFS will be asserted
2048 DMCLK cycles after
RESET
going high. The data that
is output following
RESET
and during Program Mode is ran-
dom and contains no valid information until either Data or
Mixed Mode is set.
Power Management
The individual functional blocks of the AD73311L can be
enabled separately by programming the power control register
CRC. It allows certain sections to be powered down if not
required, which adds to the device
’
s flexibility in that the user
need not incur the penalty of having to provide power for a
certain section if it is not necessary to their design. The power
control register provides individual control settings for the major
functional blocks and also a global override that allows all sec-
tions to be powered up by setting the bit. Using this method the
user could, for example, individually enable a certain section,
such as the reference (CRC:5), and disable all others. The glo-
bal power-up (CRC:0) can be used to enable all sections but if
power-down is required using the global control, the reference
will still be enabled, in this case, because its individual bit is set.
Refer to Table XIII for details of the settings of CRC.