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参数资料
| 型号： | AD73311LAR |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | Low Cost, Low Power CMOS General Purpose Analog Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO20 |
| 封装： | 0.300 INCH, SOIC-20 |
| 文件页数： | 18/36页 |
| 文件大小： | 382K |
| 代理商： | AD73311LAR |
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REV. A
AD73311L
–18–
ANALOG
LOOP-BACK
SELECT
INVERT
SINGLE-
ENDED
ENABLE
+6/
–
15dB
PGA
CONTINUOUS
TIME
LOW-PASS
FILTER
REFCAP
REFOUT
REFERENCE
0/38dB
PGA
V
REF
VINN
VINP
AD73311L
VOUTP
VOUTN
Figure 12. Analog Loop-Back Connectivity
INTERFACING
The AD73311L can be interfaced to most modern DSP engines
using conventional serial port connections and an extra enable
control line. Both serial input and output data use an accompa-
nying frame synchronization signal which is active high one
clock cycle before the start of the 16-bit word or during the last
bit of the previous word if transmission is continuous. The serial
clock (SCLK) is an output from the codec and is used to de
fi
ne
the serial transfer rate to the DSP
’
s Tx and Rx ports. Two primary
con
fi
gurations can be used: the
fi
rst is shown in Figure 13, where
the DSP
’
s Tx data, Tx frame sync, Rx data and Rx frame sync
are connected to the codec
’
s SDI, SDIFS, SDO and SDOFS,
respectively. This con
fi
guration, referred to as indirectly coupled
or nonframe sync loop-back, has the effect of decoupling the
transmission of input data from the receipt of output data. The
delay between receipt of codec output data and transmission of
input data for the codec is determined by the DSP
’
s software
latency. When programming the DSP serial port for this con-
fi
guration, it is necessary to set the Rx F
S
as an input and the Tx
F
S
as an output generated by the DSP. This con
fi
guration is
most useful when operating in mixed mode, as the DSP has the
ability to decide how many words (either DAC or control) can be
sent to the codec(s). This means that full control can be imple-
mented over the device con
fi
guration as well as updating the
DAC in a given sample interval. The second con
fi
guration
(shown in Figure 14) has the DSP
’
s Tx data and Rx data con-
nected to the codec
’
s SDI and SDO, respectively while the
DSP
’
s Tx and Rx frame syncs are connected to the codec
’
s
SDIFS and SDOFS. In this con
fi
guration, referred to as directly
coupled or frame sync loop-back, the frame sync signals are
connected together and the input data to the codec is forced to
be synchronous with the output data from the codec. The DSP
must be programmed so that both the Tx F
S
and Rx F
S
are
inputs as the codec SDOFS will be input to both. This con
fi
gura-
tion guarantees that input and output events occur simultaneously
and is the simplest con
fi
guration for operation in normal Data
Mode. Note that when programming the DSP in this con
fi
gura-
tion it is advisable to preload the Tx register with the
fi
rst control
word to be sent before the codec is taken out of reset. This
ensures that this word will be transmitted to coincide with the
fi
rst output word from the device(s).
SDIFS
SDI
SCLK
SDO
SDOFS
TFS
DT
SCLK
DR
RFS
ADSP-218x
DSP
AD73311L
CODEC
Figure 13. Indirectly Coupled or Nonframe Sync Loop-
Back Configuration
Cascade Operation
The AD73311L has been designed to support up to eight codecs
in a cascade connected to a single serial port (see Figure 37).
The SPORT interface protocol has been designed so that device
addressing is built into the packet of information sent to the device.
This allows the cascade to be formed with no extra hardware
overhead for control signals or addressing. A cascade can be
formed in either of the two modes previously discussed.
There may be some restrictions in cascade operation due to the
number of devices con
fi
gured in the cascade and the serial clock
rate chosen. Table XVII details the requirements for SCLK rate
for cascade lengths from 1 to 8 devices. This assumes a directly
coupled frame sync arrangement as shown in Figure 13.
Table XVII. Cascade Options
Number of Devices in Cascade
1
2
3
4
SCLK
5
6
7
8
DMCLK
DMCLK/2
DMCLK/4
DMCLK/8
X
X
X
X
X
X
X
X
X
X
SDIFS
SDI
SCLK
SDO
SDOFS
TFS
DT
SCLK
DR
RFS
ADSP-218x
DSP
AD73311L
CODEC
Figure 14. Directly Coupled or Frame Sync Loop-
Back Configuration
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD73311LAR-REEL | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:SINGLE-CHANNEL AFE I.C. - Tape and Reel |
| AD73311LAR-REEL7 | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:SINGLE-CHANNEL AFE I.C. - Tape and Reel |
| AD73311LARS | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin SSOP 制造商:Rochester Electronics LLC 功能描述:SINGLE-CHANNEL AFE I.C. - Bulk 制造商:Analog Devices 功能描述:IC AUDIO CODEC |
| AD73311LARS-REEL | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin SSOP T/R |
| AD73311LARSREEL7 | 制造商:AD 功能描述:New |
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