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参数资料
型号： AD73422BB-40
厂商： ANALOG DEVICES INC
元件分类： 数字信号处理
英文描述： Dual Low Power CMOS Analog Front End with DSP Microcomputer
中文描述： 24-BIT, 52 MHz, MIXED DSP, PBGA119
封装： PLASTIC, BGA-119
文件页数： 2/36页
文件大小： 396K
代理商： AD73422BB-40
REV. 0
–2–
AD73422–SPECIFICATIONS
Parameter
Min
Typ
Max
Units
Test Conditions
AFE SECTION
REFERENCE
REFCAP
Absolute Voltage, V
REFCAP
REFCAP TC
REFOUT
Typical Output Impedance
Absolute Voltage, V
REFOUT
Minimum Load Resistance
Maximum Load Capacitance
1.125 1.25
1.375
V
ppm/
°
C
50
0.1
μ
F Capacitor Required from
REFCAP to AGND2
130
1.2
V
k
pF
1.08
1
1.32
Unloaded
100
INPUT AMPLIFIER
Offset
Maximum Output Swing
±
1.0
1.578
mV
V
Max Output Swing = (1.578/1.25)
×
V
REFCAP
f
C
= 32 kHz
Feedback Resistance
Feedback Capacitance
50
100
k
pF
ANALOG GAIN TAP
Gain at Maximum Setting
Gain at Minimum Setting
Gain Resolution
Gain Accuracy
Settling Time
Delay
+1
–1
5
±
1.0
1.0
0.5
Bits
%
ms
ms
Gain Step Size = 0.0625
Output Unloaded
Tap Gain Change of –FS to +FS
ADC SPECIFICATIONS
Maximum Input Range at VIN
2, 3
1.578
–2.85
1.0954
–6.02
V p-p
dBm
V p-p
dBm
Measured Differentially.
Max Input = (1.578/1.25)
×
V
REFCAP
Measured Differentially
Nominal Reference Level at VIN
(0 dBm0)
Absolute Gain
PGA = 0 dB
PGA = 38 dB
Gain Tracking Error
Signal to (Noise + Distortion)
PGA = 0 dB
–0.5
0.4
–0.7
±
0.1
+1.2
dB
dB
dB
1.0 kHz, 0 dBm0
1.0 kHz, 0 dBm0
1.0 kHz, +3 dBm0 to –50 dBm0
72
78
78
57
56
dB
dB
dB
dB
300 Hz to 3400 Hz; f
SAMP
= 64 kHz
300 Hz to 3400 Hz; f
SAMP
= 8 kHz
0 Hz to f
SAMP
/2; f
SAMP
= 64 kHz
300 Hz to 3400 Hz; f
SAMP
= 64 kHz
55
PGA = 38 dB
Total Harmonic Distortion
PGA = 0 dB
PGA = 38 dB
Intermodulation Distortion
Idle Channel Noise
Crosstalk, ADC-to-DAC
–84
–70
–65
–71
–100
–73
dB
dB
dB
dBm0
dB
300 Hz to 3400 Hz; f
SAMP
= 64 kHz
300 Hz to 3400 Hz; f
SAMP
= 64 kHz
PGA = 0 dB
PGA = 0 dB
ADC Input Level: 1.0 kHz, 0 dBm0
DAC Input at Idle
ADC1 Input Level: 1.0 kHz, 0 dBm0
ADC2 Input at Idle. Input Amps Bypassed
Input Amplifiers Included in Input
Channel
PGA = 0 dB
Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
ADC-to-ADC
–100
dB
–70
dB
DC Offset
Power Supply Rejection
–30
+10
–65
+45
mV
dB
Group Delay
4, 5
Input Resistance at PGA
2, 4, 6
25
20
μ
s
k
DMCLK = 16.384 MHz; Input
Amplifiers Bypassed and AGT Off
DIGITAL GAIN TAP
Gain at Maximum Setting
Gain at Minimum Setting
Gain Resolution
Delay
Settling Time
+1
–1
16
25
100
Bits
ms
ms
Tested to 5 MSBs of Settings
Includes DAC Delay
Tap Gain Change from –FS to +FS;
Includes DAC Settling Time
(AVDD = DVDD = VDD = +3 V to 3.6 V; DGND = AGND = 0 V, f
DMCLK
= 16.384 MHz,
f
SAMP
= 64 kHz; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
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