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参数资料
| 型号： | AD73422BB-40 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | Dual Low Power CMOS Analog Front End with DSP Microcomputer |
| 中文描述： | 24-BIT, 52 MHz, MIXED DSP, PBGA119 |
| 封装： | PLASTIC, BGA-119 |
| 文件页数： | 21/36页 |
| 文件大小： | 396K |
| 代理商： | AD73422BB-40 |
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REV. 0
AD73422
–
21
–
There may be some restrictions in cascade operation due to the
number of devices configured in the cascade and the sampling
rate and serial clock rate chosen. The following relationship
details the restrictions in configuring a codec cascade.
Number of Codecs
×
Word Size (16)
×
Sampling Rate
≤
Serial
Clock Rate
TFS (0/1)
DT (0/1)
SCLK (0/1)
DR (0/1)
RFS (0/1)
DSP
SECTION
AFE
SECTION
CHANNEL 1
CHANNEL 2
SDIFS
SDI
SCLK2
SDO
SDOFS
AD73422
Figure 11. Directly Coupled or Frame Sync Loop-
Back Configuration
When using the indirectly coupled frame sync configuration in
cascaded operation, it is necessary to be aware of the restrictions
in sending data to all devices in the cascade. Effectively the time
allowed is given by the sampling interval (M/DMCLK, where M
can be one of 256, 512, 1024 or 2048) which is 125
μ
s for a
sample rate of 8 kHz. In this interval, the DSP must transfer
N
×
16 bits of information, where N is the number of devices in
the cascade. Each bit will take 1/SCLK and, allowing for any
latency between the receipt of the Rx interrupt and the trans-
mission of the Tx data, the relationship for successful operation
is given by:
M/DMCLK > ((N
×
16
/SCLK) + T
INTERRUPT LATENCY
)
The interrupt latency will include the time between the ADC
sampling event and the RX interrupt being generated in the
DSP—this should be 16 SCLK cycles.
As the AD73422 is configured in Cascade Mode, each device
must know the number of devices in the cascade because the
Data and Mixed modes use a method of counting input frame
sync pulses to decide when they should update the DAC
register from the serial input register. Control Register A con-
tains a 3-bit field (DC0–2) that is programmed by the DSP
during the programming phase. The default condition is that the
field contains 000b, which is equivalent to a single device in
cascade (see Table XIX). However, for cascade operation this
field must contain a binary value that is one less than the number
of devices in the cascade, which is 001b for a single AD73422
device configuration.
Table XIX. Device Count Settings
DC2
DC1
DC0
Cascade Length
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
8
FUNCTIONAL DESCRIPTION—DSP
The AD73422 instruction set provides flexible data moves and
multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single pro-
cessor cycle. The AD73422 assembly language uses an algebraic
syntax for ease of coding and readability. A comprehensive set
of development tools supports program development.
ADDRESS
BUS
HOST MODE
SERIAL PORTS
SPORT 0
SHIFTER
MAC
ALU
ARITHMETIC UNITS
MEMORY
PROGRI/O
FAND
BYTE DMA
CONTROLLER
TIMER
ADSP-2100 BASE
ARCHITECTURE
PCONTROL
SPROGRAM
DAG 2
GADATA
DAG 1
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
INDMA
PORT
(OP8K)
(OP8K)
EXDATA
BUS
FULMODE
OR
EXDATA
BUS
SPORT 1
SERIAL PORT
SPORT 2
REF
ADC2
DAC2
ADC1
DAC1
ANALOG FRONT END
SECTION
Figure 12. Functional Block Diagram
Figure 12 is an overall block diagram of the AD73422. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provi-
sions to support multiprecision computations. The ALU per-
forms a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with
40 bits of accumulation. The shifter performs logical and arith-
metic shifts, normalization, denormalization and derive expo-
nent operations.
The shifter can be used to efficiently implement numeric
format control including multiword and block floating-point
representations.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. The sequencer supports conditional jumps, sub-
routine calls and returns in a single cycle. With internal loop
counters and loop stacks, the AD73422 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four possible modify registers. A length value may be associated
with each pointer to implement automatic modulo addressing
for circular buffers.
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| AD73422BB-80 | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 119-Pin BGA 制造商:Analog Devices 功能描述:AUD CODEC 2ADC / 2DAC 16BIT 119BGA - Trays 制造商:Rochester Electronics LLC 功能描述:2CH ANALOG FRONT-END PROCESSOR +DSP I.C. - Bulk |
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