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参数资料
| 型号： | AD73422BB-40 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | Dual Low Power CMOS Analog Front End with DSP Microcomputer |
| 中文描述： | 24-BIT, 52 MHz, MIXED DSP, PBGA119 |
| 封装： | PLASTIC, BGA-119 |
| 文件页数： | 7/36页 |
| 文件大小： | 396K |
| 代理商： | AD73422BB-40 |
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REV. 0
AD73422
–7–
PBGA BALL CONFIGURATION DESCRIPTIONS
BGA
Location
T2
T1
Mnemonic
VINP1
VFBP1
Function
Analog Input to the inverting terminal of the inverting input amplifier on Channel 1’s Positive Input.
Feedback connection from the output of the inverting amplifier on Channel 1’s positive input. When the input
amplifiers are bypassed, this pin allows direct access to the positive input of Channel 1’s sigma-delta modulator.
Analog Input to the inverting terminal of the inverting input amplifier on Channel 1’s Negative Input.
Feedback connection from the output of the inverting amplifier on Channel 1’s positive input. When the input
amplifiers are bypassed, this pin allows direct access to the negative input of Channel 1’s sigma-delta modulator.
Buffered Reference Output, which has a nominal value of 1.2 V. As the reference is common to the two
codec units, the reference value is set by the wired OR of the CRC:7 bits in each codec’s status register.
A Bypass Capacitor to AGND2 of 0.1
μ
F is required for the on-chip reference. The capacitor should be
fixed to this pin.
AFE Digital Ground/Substrate Connection.
AFE Digital Power Supply Connection.
Active Low Reset Signal. This input resets the entire chip, resetting the control registers and clearing the
digital circuitry.
Output Serial Clock whose rate determines the serial transfer rate to/from the codec. It is used to clock data
or control information to and from the serial port (SPORT). The frequency of SCLK is equal to the fre-
quency of the master clock (AMCLK) divided by an integer number—this integer number being the prod-
uct of the external master clock rate divider and the serial clock rate divider.
AFE Master Clock Input. AMCLK is driven from an external clock signal. If it is required to run the DSP
and AFE sections from a common clock crystal, AMCLK should be connected to the XTAL pin of the
DSP section.
Serial Data Output of the Codec. Both data and control information may be output on this pin and is clocked on
the positive edge of SCLK. SDO is in three-state when no information is being transmitted and when SE is low.
Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and is active one SCLK
period before the first bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK.
SDOFS is in three-state when SE is low.
Framing Signal Input for SDI Serial Transfers. The frame sync is one bit wide and is valid one SCLK pe-
riod before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK and is
ignored when SE is low.
Serial Data Input of the Codec. Both data and control information may be input on this pin and are clocked
on the negative edge of SCLK. SDI is ignored when SE is low.
SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the out-
put pins of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled internally in
order to decrease power dissipation. When SE is brought high, the control and data registers of the SPORT
are at their original values (before SE was brought low), however the timing counters and other internal
registers are at their reset values.
AFE Analog Ground/Substrate Connection.
AFE Analog Power Supply Connection.
Analog Output from the Positive Terminal of Output Channel 2.
Analog Output from the Negative Terminal of Output Channel 2.
Analog Output from the Positive Terminal of Output Channel 1.
Analog Output from the Negative Terminal of Output Channel 1.
Analog Input to the inverting terminal of the inverting input amplifier on Channel 2’s Positive Input.
Feedback connection from the output of the inverting amplifier on Channel 2’s positive input. When the input
amplifiers are bypassed, this pin allows direct access to the positive input of Channel 2’s sigma-delta modulator.
Analog Input to the inverting terminal of the inverting input amplifier on Channel 2’s Negative Input.
Feedback connection from the output of the inverting amplifier on Channel 2’s Negative Input. When the input
amplifiers are bypassed, this pin allows direct access to the negative input of Channel 2’s sigma-delta modulator.
(Input) Processor Reset Input.
(Input) Bus Request Input.
(Output) Bus Grant Output.
(Output) Bus Grant Hung Output.
(Output) Data Memory Select Output.
(Output) Program Memory Select Output.
(Output) Memory Select Output.
(Output) Byte Memory Select Output.
(Output) Combined Memory Select Output.
(Output) Memory Read Enable Output.
(Output) Memory Write Enable Output.
(Input) Edge- or Level-Sensitive Interrupt Request
1
.
(Input/Output)
Programmable I/O Pin.
(Input) Level-Sensitive Interrupt Requests
1
.
(Input/Output) Programmable I/O Pin.
VINN1
VFBN1
T4
T3
REFOUT
R7
REFCAP
R6
DGND
DVDD
ARESET
P4
P3
P5
SCLK2
P6
AMCLK
P7
SDO
R1
SDOFS
R2
SDIFS
R3
SDI
R4
SE
R5
AGND
AVDD
VOUTP2
VOUTN2
VOUTP1
VOUTN1
VINP2
VFBP2
U1
U2
U3
U4
U5
U6
U7
T7
VINN2
VFBN2
T6
T5
RESET
BR
BG
BGH
DMS
PMS
IOMS
BMS
CMS
RD
WR
IRQ2/
PF7
IRQL1/
PF6
H3
N1
L1
F5
A2
B2
C2
D3
D2
C3
B3
D1
C1
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