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参数资料
| 型号： | AD73422BB-40 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | Dual Low Power CMOS Analog Front End with DSP Microcomputer |
| 中文描述： | 24-BIT, 52 MHz, MIXED DSP, PBGA119 |
| 封装： | PLASTIC, BGA-119 |
| 文件页数： | 23/36页 |
| 文件大小： | 396K |
| 代理商： | AD73422BB-40 |
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REV. 0
AD73422
–
23
–
Full Memory Mode Pins (Mode C = 0)
Pin
# of
Input/
Name(s)
Pins
Output Function
A13:0
14
O
Address Output Pins for Program,
Data, Byte and I/O Spaces
Data I/O Pins for Program, Data,
Byte and I/O Spaces (8 MSBs are
also used as Byte Memory
addresses)
D23:0
24
I/O
Host Mode Pins (Mode C = 1)
Pin
# of
Name(s)
Pins
Input/
Output Function
IAD15:0
A0
16
1
I/O
O
IDMA Port Address/Data Bus
Address Pin for External I/O,
Program, Data or Byte Access
Data I/O Pins for Program, Data
Byte and I/O Spaces
IDMA Write Enable
IDMA Read Enable
IDMA Address Latch Pin
IDMA Select
IDMA Port Acknowledge Configur-
able in Mode D; Open Source
D23:8
16
I/O
IWR
IRD
IAL
IS
IACK
1
1
1
1
1
I
I
I
I
O
NOTE
In Host Mode, external peripheral addresses can be decoded using the A0,
CMS
,
PMS
,
DMS
and
IOMS
signals.
Terminating Unused Pin
The following table shows the recommendations for terminating
unused pins.
Pin Terminations
I/O
3-State
(Z)
Hi-Z*
Caused
By
Pin
Name
Reset
State
Unused
Configuration
XTAL
CLKOUT
A13:1 or
IAD12:0
A0
D23:8
D7 or
IWR
D6 or
IRD
D5 or
IAL
D4 or
IS
D3 or
IACK
D2:0 or
IAD15:13
PMS
DMS
BMS
IOMS
I
O
O (Z)
I/O (Z)
O (Z)
I/O (Z)
I/O (Z)
I
I/O (Z)
I
I/O (Z)
I
I/O (Z)
I
I/O (Z)
I
O
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
I
Hi-Z
I
Hi-Z
I
Hi-Z
I
Hi-Z
Float
Float
Float
Float
Float
Float
Float
High (Inactive)
Float
High (Inactive)
Float
Low (Inactive)
Float
High (Inactive)
Float
Float
Float
Float
Float
Float
Float
Float
BR
,
EBR
IS
BR
,
EBR
BR
,
EBR
BR
,
EBR
BR
,
EBR
BR
,
EBR
BR
,
EBR
BR
,
EBR
I/O (Z)
I/O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
Hi-Z
Hi-Z
O
O
O
O
BR
,
EBR
IS
BR
,
EBR
BR
,
EBR
BR
,
EBR
BR
,
EBR
Pin Terminations (Continued)
I/O
3-State
(Z)
Hi-Z*
Caused
By
Pin
Name
Reset
State
Unused
Configuration
CMS
RD
WR
BR
BG
BGH
IRQ2
/PF7
O (Z)
O (Z)
O (Z)
I
O (Z)
O
I/O (Z)
O
O
O
I
O
O
I
BR
,
EBR
BR
,
EBR
BR
,
EBR
Float
Float
Float
High (Inactive)
Float
Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High or Low,
Output = Float
High or Low
High or Low
High or Low
Float
Input = High or Low,
Output = Float
High or Low
High or Low
High or Low
Float
EE
IRQL1
/PF6 I/O (Z)
I
IRQL0
/PF5 I/O (Z)
I
IRQE
/PF4
I/O (Z)
I
SCLK0
I/O
I
RFS0
DR0
TFS0
DT0
SCLK1
I/O
I
I/O
O
I/O
I
I
O
O
I
RFS1/
IRQ0
I/O
DR1/FI
TFS1/
IRQ1
I/O
DT1/FO
EE
EBR
EBG
ERESET
EMS
EINT
ECLK
ELIN
ELOUT
I
I
O
O
I
I
O
I
O
I
I
I
O
I
O
I
I
O
I
O
I
I
I
O
NOTES
*Hi-Z = High Impedance.
1. If the CLKOUT pin is not used, turn it OFF.
2. If the Interrupt/Programmable Flag pins are not used, there are two options:
Option 1: When these pins are configured as INPUTS at reset and function
as interrupts and input flag pins, pull the pins High (inactive).
Option 2: Program the unused pins as OUTPUTS, set them to 1, and let
them float.
3. All bidirectional pins have three-stated outputs. When the pins is configured
as an output, the output is Hi-Z (high impedance) when inactive.
4. CLKIN, RESET, and PF3:0 are not included in the table because these pins
must be used.
Interrupts
The interrupt controller allows the processor to respond to the
eleven possible interrupts and
RESET
with minimum overhead.
The AD73422 provides four dedicated external interrupt
input pins,
IRQ2
,
IRQL0
,
IRQL1
and
IRQE
. In addition,
SPORT1 may be reconfigured for
IRQ0
,
IRQ1
, FLAG_IN
and FLAG_OUT, for a total of six external interrupts. The
AD73422 also supports internal interrupts from the timer, the
byte DMA port, the two serial ports, software and the power-
down control circuit. The interrupt levels are internally priori-
tized and individually maskable (except power-down and reset).
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